3D Semiconductor Device With Nanoscale Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in wafer alignment, TSV density, and temperature constraints, leading to inefficiencies in interconnects and reliability, particularly in monolithic 3D IC construction methods.
Innovation Solution
The development of a 3D semiconductor device with a layered structure using single crystal silicon transistors and through-layer vias (TLVs) with diameters less than 400 nm, enabling high-density interconnects and low-temperature processing to overcome alignment and temperature limitations, while maintaining reliability through oxide-to-oxide bonding and ion-cut layer transfer techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Through Silicon Vias (TSVs) are used for interconnects, then vertical connections between layers are achieved, but the density is limited due to large diameter requirements (1-10 microns) for alignment tolerance
Solution Approach 1:
The patent transitions from conventional planar 2D integration to 3D vertical integration by stacking multiple transistor layers and interconnect layers vertically. This dimensional change enables significantly higher device density by utilizing the third dimension (vertical stacking) rather than only expanding in the planar direction, allowing millions of interconnections per chip compared to the 10,000s per chip achievable with TSVs.
Solution Approach 2:
The patent changes the critical dimension parameter from micron-scale TSV diameters (1-10 microns) to nanometer-scale via diameters (5-400 nm). This parameter change in feature size enables dramatically higher interconnect density while the oxide-to-oxide bonding and ion-cut techniques provide the necessary alignment precision to achieve such small dimensions.
2Quantity of substance
If monolithic 3D IC construction is used, then integration density is increased, but temperature constraints limit processing and reliability
Solution Approach 1:
The patent segments the fabrication process into distinct stages: low-temperature oxide-to-oxide bonding to attach thin silicon layers to a handle wafer, followed by high-temperature processing after layer transfer. This segmentation allows the temperature-sensitive bonding step to occur at low temperature while subsequent high-temperature processing occurs after the structure is already assembled, resolving the contradiction between integration density and temperature constraints.
Solution Approach 2:
The patent performs preliminary low-temperature oxide-to-oxide bonding to attach the thin silicon layer to the handle wafer before conducting high-temperature processing. This preliminary action at low temperature establishes the structural foundation, allowing subsequent high-temperature steps to proceed without compromising the temperature-sensitive bonded interface, thereby enabling high integration density while managing temperature constraints.
3Quantity of substance
If thin silicon layers are used for high-density integration, then interconnect density improves, but handling and processing becomes difficult and yield is reduced
Solution Approach 1:
The patent introduces a thick oxide layer and a handle wafer as intermediary structures to support the thin silicon layer during fabrication and processing. The handle wafer provides mechanical strength and handling capability, while the oxide layer serves as both structural support and a bonding interface. This intermediary approach enables the use of thin silicon layers for high density while maintaining ease of manufacture through the robust handle wafer support.
Solution Approach 2:
The patent applies local quality by having different thicknesses and properties in different parts of the structure: a thin silicon layer (5-2000 nm) for high-density device integration, a thick oxide layer for structural support and bonding, and a thick handle wafer for mechanical strength. Each layer is optimized locally for its specific function, enabling both high interconnect density and ease of handling.
4Quantity of substance
If via diameter is reduced to increase density, then interconnect density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces conventional mechanical alignment methods with oxide-to-oxide bonding, where the alignment is achieved through chemical bonding of oxide surfaces rather than mechanical positioning. This substitution enables nanometer-scale alignment precision (5-400 nm via diameters) because the oxide bonding process inherently provides self-alignment and tolerance to misalignment, allowing extremely high via density without proportionally increasing alignment difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance and density, reduces power consumption, and increases yield by enabling shorter interconnects and more complex logic integration within a smaller form factor, suitable for mobile electronics and other high-complexity applications.
Implementation Method 1
bonding the thin silicon layer to the handle wafer through an oxide layer
Implementation Method 2
subsequently removing a sacrificial layer from the thin silicon layer with an ion beam
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via has a diameter of less than 400 nm and greater than 5 nm.