3D Semiconductor Structure With Nested Channel-Source Contact
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Solution Overview
Problem
The challenge of further reducing the size of semiconductor structures while maintaining performance is exacerbated by the difficulty in miniaturizing traditional planar MOS transistors.
Innovation Solution
A semiconductor structure design featuring a source layer with depressions and a channel layer partially filled into these depressions, along with a gate dielectric layer and a gate structure, optimizing vertical space utilization and enhancing conductivity reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional planar MOS transistor structure is used, then manufacturing process is simple, but geometric size cannot be further reduced
Solution Approach 1:
The patent transitions from a traditional planar two-dimensional layout to a three-dimensional stacked structure. The source layer and drain layer are positioned at different vertical levels, with the channel layer connecting them, creating a vertical current path. This dimensional change enables further size reduction in the planar footprint while maintaining transistor functionality.
Solution Approach 2:
The patent implements a nested structure where the channel layer is partially filled into depressions formed in the source layer. The gate structure is then formed on the side wall of the channel layer, creating a nested arrangement where each component is positioned within or around the previous component, maximizing space utilization and reducing overall device footprint.
2Productivity
If size is reduced, then integration density increases, but performance may deteriorate
Solution Approach 1:
The patent applies local quality by creating depressions in the source layer with specific contour shapes (arc-shaped or U-shaped) to optimize the interface between the source layer and channel layer. The gate dielectric layer is selectively positioned in direct contact with the channel layer at critical locations, providing enhanced electrical characteristics where needed while maintaining overall device compactness.
Solution Approach 2:
The patent specifies that the contour shape of the depression is arc-shaped or U-shaped, using curved geometries instead of sharp angles. This curvature design reduces stress concentration at corners and improves the electrical field distribution at the source-channel interface, thereby maintaining transistor performance despite the reduced device size.
3Area of stationary object
If vertical stacking is implemented, then footprint area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by pre-forming depressions in the source layer with specific shapes and dimensions before depositing the channel layer. These pre-formed features serve as templates that guide subsequent material deposition and self-align the channel layer, reducing the need for high-precision alignment steps and simplifying the manufacturing process despite the three-dimensional structure.
Data Source
AI summary
A semiconductor structure and a preparation method therefor, which relate to the field of semiconductor technology. The semiconductor structure includes a substrate, a source layer, a drain layer, a channel layer, a gate structure, a gate dielectric layer, and a dielectric layer. The source layer and the drain layer are stacked disposed on the substrate. The channel layer is located between the source layer and the drain layer. The gate structure is located on a side wall of the channel layer. The gate dielectric layer is located between the gate structure and the channel layer. A portion of the dielectric layer is arranged between the source layer and the gate structure. The source layer has a plurality of depressions extending towards the substrate, and the channel layer is partially filled into the depressions and electrically connected to the source layer.