3D Semiconductor Device with Nested TSV Interconnects
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through Silicon Via (TSV) sizes, which restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) to construct configurable logic, allowing for the creation of multiple layers with precise alignment and reduced lithography steps, enabling the integration of various memory blocks and logic functions, and utilizing a modular approach with Through-Silicon-Via (TSV) to connect different dies fabricated in different processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent segments the fabrication process into modular stages: forming mandrels, depositing sacrificial layers, creating voids, and filling with functional materials. This modular approach allows different logic families to be produced by changing only specific process modules rather than requiring complete mask set redesigns, thereby reducing costs while maintaining flexibility.
Solution Approach 2:
The patent introduces re-programmable antifuse technology that allows the logic device to be dynamically reconfigured after fabrication. This dynamic capability enables the same physical device to adapt to different logic functions without requiring new mask sets, significantly improving flexibility while avoiding the costs of multiple mask sets.
2Productivity
If existing 3D IC technologies are used, then connections between dies are established, but TSV sizes are large which restricts the number of connections
Solution Approach 1:
The patent implements a nested structure where multiple conductive elements are placed within and around the TSV. The TSV contains an inner conductive element, which is surrounded by an intermediate dielectric layer, which is in turn surrounded by an outer conductive element. This nested arrangement allows multiple functional connections to be achieved within a single TSV footprint, effectively increasing the number of connections without increasing TSV size.
Solution Approach 2:
The patent transitions from two-dimensional connection planning to three-dimensional connection architecture. By utilizing the vertical dimension within the TSV structure and arranging conductive elements at different heights and radial positions, the patent maximizes the number of connections that can be achieved through each TSV, effectively overcoming the limitation of large TSV sizes.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.