3D Semiconductor Device with Optical Annealing
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Solution Overview
Problem
The semiconductor industry faces challenges in constructing high-density connections between layers of 3D stacked semiconductor chips due to misalignment issues and the degradation of wiring layers when forming transistors at high temperatures, leading to limited connectivity and performance degradation.
Innovation Solution
A 3D semiconductor device architecture that includes multiple levels of transistors and metal layers with polysilicon channels, where the top transistors are processed at temperatures above 400°C without damaging underlying wiring layers, and uses optical annealing to repair defects and activate dopants, enabling high-density connectivity and improved heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors are constructed at high temperatures (higher than 700°C) to achieve proper transistor formation, then transistor performance and density improve, but underlying wiring layers (constructed at temperatures lower than 400°C) get damaged
Solution Approach 1:
The patent divides the transistor formation process into multiple sequential stages with different temperature requirements. The first stage forms the transistor channel at lower temperature to protect wiring, while subsequent stages complete transistor formation at higher temperatures, thereby resolving the contradiction between achieving proper transistor formation and protecting underlying wiring layers
Solution Approach 2:
The patent performs preliminary actions by forming the transistor channel structure at lower temperatures before the wiring layers are fully constructed or before high-temperature processing occurs. This preliminary channel formation protects the wiring layers from damage while still enabling subsequent high-temperature transistor optimization
2Manufacturing precision
If 3D stacking is implemented to reduce wire lengths and improve density, then transistor proximity improves, but alignment precision and contact density deteriorate due to misalignment issues
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-oriented transistors, utilizing the vertical dimension to achieve high density while maintaining alignment precision through self-aligned fabrication processes that eliminate misalignment issues between layers
3Reliability
If contact size is increased to compensate for misalignment during wafer bonding, then alignment tolerance improves, but contact density and connectivity decrease
Solution Approach 1:
The patent moves contacts from the planar dimension to the vertical dimension through self-aligned via formation processes, enabling precise alignment without requiring large contact areas, thereby maintaining high contact density while achieving sufficient alignment tolerance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the construction of high-density 3D semiconductor devices with improved connectivity and performance by preventing damage to wiring layers during transistor formation and enhancing heat management, thereby overcoming the limitations of existing 3D stacking technologies.
Implementation Method 1
uses optical annealing to repair defects and activate dopants
Data Source
AI summary
A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.