3D Semiconductor Device With Orthogonal Fin Etch Mask
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Solution Overview
Problem
The manufacturing of three-dimensional (3D) semiconductor devices is hindered by high costs and complex processes compared to two-dimensional (2D) devices, as the integration density in 3D devices is achieved at the expense of increased difficulty and cost, necessitating a simpler and more cost-effective fabrication method.
Innovation Solution
A method involving the use of a first set of fins and a second set of fins with sidewall spacers as etch masks to form transistor structures, allowing for a reduced number of mask layers and enabling access and processing from multiple directions, thereby simplifying the manufacturing process of 3D semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional manufacturing methods are used for 3D semiconductor devices, then integration density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple mask layers into a single mask structure that defines fins, source/drain regions, and channel regions simultaneously. This is achieved by forming a mask layer with a specific pattern that is then etched to create all necessary features in one process step, eliminating the need for separate masking operations for each feature type.
Solution Approach 2:
The mask structure serves multiple functions: it defines the fins, defines the source/drain regions through sidewall spacer formation, and defines the channel regions through subsequent etching. This multi-functional mask eliminates the need for separate specialized masks for each feature, reducing overall manufacturing complexity.
2Manufacturing precision
If multiple mask layers are used per transistor, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Multiple mask layers are merged into a single mask structure that is formed once and then used to define all critical features including fins, source/drain regions, and channel regions. This consolidation maintains manufacturing precision while eliminating the complexity of stacking multiple mask layers.
Solution Approach 2:
The patent transitions from a planar 2D mask approach to a 3D mask structure with fins extending vertically. This dimensional change allows a single mask to define features in multiple spatial dimensions simultaneously, reducing the number of mask layers needed while maintaining precision.
Data Source
AI summary
The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs.