3D Semiconductor Devices with Oxide-to-Oxide Bonding
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Solution Overview
Problem
Current 3D stacked semiconductor chip technologies face challenges in achieving high-density connections between layers due to misalignment issues and the need for high-temperature processing, which damages lower wiring layers and limits connectivity.
Innovation Solution
The method involves constructing 3D memory devices with single crystal transistors and layers using alignment marks, etching lithography windows, and performing multiple lithographic and etch steps to form memory cells, while using oxide-to-oxide bonding and layer transfer techniques to achieve high-density connectivity without degrading existing layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing (>700°C) is used to construct transistor layers, then transistor performance and density improve, but lower wiring layers are damaged
Solution Approach 1:
The patent divides the semiconductor structure into separate levels: a first level with transistors constructed at high temperature, and a second level with wiring constructed at lower temperature. This segmentation allows each layer to be optimized for its specific temperature requirements, resolving the contradiction between transistor performance and wiring integrity.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical stacking, placing transistor layers and wiring layers at different vertical levels. This dimensional change enables independent temperature processing of each layer type, allowing high-temperature transistor fabrication without damaging sensitive wiring layers.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but alignment precision and connectivity density are limited
Solution Approach 1:
The patent incorporates alignment marks at predetermined locations on the substrate before constructing transistor and wiring layers. These pre-positioned marks enable precise alignment between stacked levels, overcoming the limitations of conventional alignment methods and achieving high connectivity density in 3D stacked structures.
3Reliability
If copper or aluminum wiring levels are used, then electrical conductivity improves, but they get damaged when exposed to temperatures higher than 400°C
Solution Approach 1:
The patent separates the fabrication processes for conductive wiring layers from high-temperature transistor processing by constructing wiring at lower temperatures on a second level, after or independent of high-temperature transistor formation on the first level. This temporal and spatial segmentation protects temperature-sensitive wiring materials while maintaining electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of 3D semiconductor devices with high-density connections and reliable transistor performance across layers, overcoming the limitations of existing technologies by allowing for high-temperature processing of transistors without damaging lower wiring layers.
Implementation Method 1
performing bonding of the first level to the second level, wherein the bonding comprises oxide to oxide bonding
Implementation Method 2
performing a first lithographic step over the at least one second level aligned to the first alignment marks; performing a second lithographic step over the third level; performing a third lithographic step over the at least one third level
Implementation Method 3
performing a first etch step including etching holes within the third level defined by the second lithographic step; performing a second etch step including etching holes within the at least one third level and the at least one second level defined by the third lithographic step
Data Source
AI summary
A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.