3D Semiconductor Device With Oxide-to-Oxide Bonding
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Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges due to the degradation of wiring performance with scaling, limited connectivity between layers, and the difficulty of constructing transistors above wiring layers at high temperatures without damaging the lower wiring layers, leading to low connectivity and high power consumption.
Innovation Solution
The development of 3D semiconductor devices with horizontally oriented transistors and oxide-to-oxide bonding, allowing for the construction of multiple layers with single-crystal silicon and high-density connectivity using ion-cut layer transfer techniques and shared lithography steps to align transistors and bonding marks, enabling efficient 3D integration without the need for high-temperature processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed in 3 dimensions along with wires using high temperatures (>700°C), then transistor performance and density improve, but the bottom wiring layer gets damaged
Solution Approach 1:
The patent divides the 3D integration process into separate stages: first forming the bottom wiring layer at low temperature, then adding transistor layers at high temperature, and finally connecting them through low-temperature processes. This segmentation allows each layer to be optimized for its specific temperature requirements without damaging other layers.
Solution Approach 2:
The patent introduces intermediate structures such as bonding interfaces and transition layers that mediate between the high-temperature transistor formation process and the low-temperature wiring layer. These intermediaries protect the sensitive wiring from thermal damage while enabling 3D integration.
2Ease of manufacture
If alternative 3D stacking architectures are used with wafer bonding, then transistor layers can be constructed separately, but connectivity between layers is limited to few thousand connections
Solution Approach 1:
The patent transitions from 2D planar connections to 3D vertical connections through the introduction of through-silicon vias (TSVs) and vertical interconnect structures. This dimensional change enables high-density inter-layer connectivity by utilizing the vertical space between stacked wafers, allowing billions of connections instead of thousands.
3Manufacturing precision
If contact landing pad size is increased to accommodate alignment issues, then alignment tolerance improves, but contact density and connectivity decrease
Solution Approach 1:
The patent performs preliminary alignment mark formation and registration processes before final contact fabrication. By establishing alignment references in advance and using them to guide subsequent processing steps, the system achieves high precision without requiring oversized contact pads, thereby maintaining high contact density.
4Productivity
If Through-Silicon Via (TSV) dimensions are reduced to increase density, then contact density improves, but etching and filling difficulty increases
Solution Approach 1:
The patent systematically optimizes TSV parameters including diameter, depth, wall thickness, and filling material properties to achieve the desired density while maintaining manufacturability. By carefully controlling these parameters and their relationships, the patent enables high-density TSV arrays that can be successfully etched and filled using available fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density connectivity and reliable 3D integration with reduced power consumption by maintaining transistor and wiring reliability across layers, overcoming the limitations of existing technologies in 3D chip stacking.
Implementation Method 1
wherein said second level is bonded to said first level, and wherein said bonded comprises oxide to oxide bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.