3D Semiconductor Device with Oxide-to-Oxide Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges due to the degradation of wiring performance with scaling, limited connectivity between layers, and the need for high-temperature processing that damages lower wiring layers, leading to low connectivity and reliability issues.
Innovation Solution
The development of 3D semiconductor devices with horizontally oriented transistors and oxide-to-oxide bonding, using single crystal layers and alignment marks to achieve high-density connections and self-aligned processing, allowing for high-temperature processing of transistors without degrading lower layers, and employing ion-cut and layer transfer techniques for monocrystalline silicon layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing (>700°C) is used to construct transistor layers, then transistor performance and density improve, but lower wiring layers are damaged
Solution Approach 1:
The patent transitions from planar 2D integration to 3D vertical stacking, allowing transistors to be positioned above wiring layers in the vertical dimension. This enables high-temperature transistor processing without exposing the wiring layers to damaging temperatures, as they occupy different vertical levels in the stacked architecture.
Solution Approach 2:
The patent divides the integrated circuit into separate functional layers: transistor layers and wiring layers, stacked vertically. This segmentation allows independent processing of each layer at appropriate temperatures - transistors can be formed at high temperatures in their dedicated layers while wiring layers are processed at lower temperatures separately, avoiding cross-contamination of thermal effects.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but connectivity between layers is limited
Solution Approach 1:
The patent implements multiple wiring layers nested within the vertical stack, with each level providing additional interconnection pathways. This nested multi-layer wiring architecture dramatically increases the number of available connections between layers compared to simple through-silicon via approaches, enabling high-density 3D integration with billions of potential inter-layer connections.
3Reliability
If through-silicon via contacts are used for layer connections, then direct electrical connection is achieved, but contact size must be large and alignment precision is reduced
Solution Approach 1:
The patent introduces alignment marks as intermediary features that facilitate precise registration between stacked layers. These marks serve as reference points that guide the bonding process, enabling sub-micron alignment accuracy even when dealing with large contact pads, thereby resolving the conflict between contact size and alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of 3D integrated circuits with high-density connections and improved reliability by maintaining the integrity of lower wiring layers, enhancing performance and connectivity while allowing for high-temperature processing of transistors without compromising the characteristics of lower layers.
Implementation Method 1
wherein said second level is bonded to said first level, and wherein said bonded comprises oxide to oxide bonds
Implementation Method 2
employing ion-cut and layer transfer techniques for monocrystalline silicon layers
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and include replacement gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.