3D Semiconductor Package Layout for Short Die-to-Die Paths
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in efficiently integrating multiple semiconductor dies and achieving a short electrical path, which leads to signal loss and increased complexity in wafer level packaging.
Innovation Solution
The proposed solution involves a manufacturing method for a semiconductor package that includes forming a redistribution circuit structure on a carrier, placing semiconductor dies on the redistribution circuit structure, and using a chip package with multiple semiconductor dies electrically connected to each other, which is then stacked and encapsulated to create a compact and efficient electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor dies are integrated at wafer level, then packaging efficiency is improved, but electrical path length increases causing signal loss
Solution Approach 1:
The patent transitions from planar wafer-level integration to three-dimensional stacked packaging. Multiple semiconductor dies are vertically stacked and interconnected through redistribution circuit structures, changing the integration geometry from two-dimensional to three-dimensional. This dimensional change enables shorter electrical paths between dies while maintaining high packaging density, thereby improving both productivity and reducing signal loss.
2Ease of manufacture
If wafer level packaging is used, then manufacturing complexity is reduced, but electrical connection length increases
Solution Approach 1:
The patent implements nested packaging structures where chip packages containing multiple semiconductor dies are stacked and interconnected. The redistribution circuit structures are embedded within the stack, with lower redistribution layers connecting to lower dies and upper redistribution layers connecting to upper dies. This nesting approach enables short electrical paths through vertical interconnections while maintaining manufacturing simplicity through standardized packaging processes.
Data Source
AI summary
A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.