3D Semiconductor Device with Polysilicon Channels
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Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges due to the degradation of wiring performance and low connectivity between layers, primarily because of the mismatch in processing temperatures required for transistor and wiring layers, leading to misalignment and defects in contact formation.
Innovation Solution
The development of 3D semiconductor devices with single-crystal layers and junction-less transistors, where transistors are constructed using polysilicon channels and processed at temperatures below 400°C, allowing for high-density connectivity and alignment of multiple transistor layers without degrading existing layers, utilizing techniques like ion-cut layer transfer and shared lithography for improved alignment and defect reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed at high temperatures (>700°C) to achieve good transistor performance, then transistor quality is improved, but existing wiring layers are damaged due to thermal degradation
Solution Approach 1:
The invention divides the transistor fabrication process into separate temperature stages: forming the transistor channel at high temperature (>700°C) followed by forming wiring layers at low temperature (<400°C). This temporal and thermal segmentation allows each layer to be processed at its optimal temperature without damaging other layers, resolving the contradiction between transistor quality and wiring layer integrity
Solution Approach 2:
The transistor channel is formed in advance at high temperature before the wiring layers are deposited. This preliminary action allows the transistor structure to be established with optimal crystal quality while subsequent low-temperature wiring processes preserve the integrity of already-formed layers, preventing thermal damage to wiring
2Reliability
If 3D stacking is implemented to reduce wire lengths and improve connectivity, then wiring performance is improved, but alignment precision deteriorates due to wafer bonding misalignment
Solution Approach 1:
The invention replaces mechanical wafer bonding alignment with a self-aligned approach where transistors and wiring are formed in a monolithic 3D structure using the same lithography and etching processes. This substitution of mechanical alignment with process-integrated alignment eliminates misalignment issues while maintaining high connectivity in the 3D stacked architecture
Solution Approach 2:
The invention merges the formation of transistors and wiring layers into a unified monolithic 3D fabrication process where both structures are created simultaneously or sequentially in the same process flow. This merging ensures automatic alignment between transistor gates and wiring connections, achieving high manufacturing precision while maintaining the 3D stacking benefits
3Adaptability or versatility
If Through-Silicon Via (TSV) contacts are used to connect stacked wafers, then connectivity between layers is achieved, but contact density is limited due to large contact size requirements
Solution Approach 1:
The invention transitions from 2D planar contacts to 3D vertically-integrated contacts where wiring layers extend through multiple transistor layers in the vertical dimension. This dimensional change allows numerous wiring connections to pass through the stack without requiring large lateral contact areas, dramatically increasing contact density while maintaining full connectivity between layers
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.