3D Semiconductor Power Grids for Thermal Management
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Solution Overview
Problem
Three-dimensional integrated circuits (3D-ICs) face significant challenges in heat removal due to increased power density and high thermal resistance, particularly in stacked configurations where heat transfer from semiconductor layers to heat sinks is inefficient, often relying on ineffective materials like insulating oxides and dielectrics that do not conduct heat well.
Innovation Solution
The implementation of thermally conductive materials and structures, such as heat spreaders, thermally conductive shallow trench isolation, pre-metal dielectric regions, and etch stop layers, along with thermal contacts and vias, to enhance heat transfer pathways and reduce thermal resistance within the 3D-ICs, allowing for more effective heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3D stacking of semiconductor devices is implemented to reduce wire lengths and improve transistor density, then transistor performance and integration density improve, but heat removal efficiency deteriorates due to increased power density and high thermal resistance
Solution Approach 1:
The patent segments the heat removal function by introducing separate thermal pathways through thermal vias that are distinct from power and ground vias. This segmentation allows dedicated thermal management channels to be created, enabling heat to be removed efficiently without interfering with electrical power distribution. The thermal vias are distributed throughout the device structure to segment heat removal across multiple locations.
Solution Approach 2:
The patent transitions from 2D heat removal to 3D heat removal by implementing vertical thermal pathways through the stacked device layers. Thermal vias extend in the vertical dimension through multiple device layers and interconnect layers, creating three-dimensional thermal management that matches the 3D architecture of the integrated circuit. This dimensional transition allows heat to be conducted vertically to heat sinks positioned on the opposite surface of the device stack.
2Power
If multiple device layers are stacked to increase power density, then functionality and performance improve, but thermal resistance to heat sink increases making heat removal more difficult
Solution Approach 1:
The patent introduces thermal vias as intermediary structures that facilitate heat transfer between device layers and heat sinks. These thermal vias act as thermal conduits or mediators, providing low-resistance thermal pathways that bridge the thermal gap created by multiple stacked layers. The thermal vias are filled with thermally conductive materials that mediate the heat transfer process, reducing the overall thermal resistance of the stacked structure.
Solution Approach 2:
The patent employs composite material structures combining different materials with complementary properties. Thermal vias are filled with thermally conductive materials such as metals or metal alloys that provide low thermal resistance. The via structures themselves may comprise composite constructions including conductive fillers in matrix materials, creating composite thermal pathways that optimize heat conduction while maintaining structural integrity and electrical isolation.
3Reliability
If conventional insulating materials are used in 3D stacked devices, then electrical isolation is achieved, but heat conduction is blocked reducing heat removal efficiency
Solution Approach 1:
The patent applies local quality by creating spatially differentiated material properties. In regions where electrical isolation is needed, insulating materials are used. In regions where heat removal is critical, thermal vias filled with thermally conductive materials are implemented. This local differentiation allows simultaneous achievement of electrical isolation and thermal conduction by optimizing material selection for specific functional requirements at different locations within the device structure.
Solution Approach 2:
The thermal vias serve as intermediary structures that decouple the electrical and thermal functions. These vias provide thermal conduction pathways while maintaining electrical isolation through their construction and positioning. The intermediary thermal via structures enable heat to pass through regions where electrical signals must remain isolated, resolving the conflict between electrical insulation and thermal conduction requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These measures significantly improve heat removal efficiency by creating conductive pathways that can efficiently transfer heat from transistors to heat sinks, maintaining desirable temperature levels across the 3D-ICs and reducing thermal resistance, thus addressing the heat management issues in 3D stacked devices.
Implementation Method 1
a first thermal contact extending from a first power distribution interconnect to the first semiconductor layer, the first thermal contact having a first thermal conductivity; a second thermal contact extending from a second power distribution interconnect to the second semiconductor layer, the second thermal contact having a second thermal conductivity
Implementation Method 2
heat spreaders, thermally conductive shallow trench isolation, pre-metal dielectric regions, and etch stop layers, along with thermal contacts and vias, to enhance heat transfer pathways
Implementation Method 3
Thermal vias have been suggested as techniques to transfer heat from stacked device layers to the heat sink
Implementation Method 4
Publications have suggested passing liquid coolant through multiple device layers of a 3D-IC to remove heat
Data Source
AI summary
A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.