3D Semiconductor Power Distribution Planes for Density and Resistance
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Solution Overview
Problem
Conventional power distribution networks in monolithic 3D semiconductor IC devices occupy significant area and have high resistance, limiting integration density and increasing power dissipation due to the use of parallel power busses and lateral connections.
Innovation Solution
Implementing power distribution planes below, between, or above device tiers to distribute positive and negative power supply voltage, utilizing backside, inter-tier, and back-end-of-line power distribution planes with metallic plates and contact pads isolated by insulating spacers, to reduce area occupation and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional parallel power busses and lateral connections are used in device layout cells, then power distribution can be achieved, but area occupation increases and integration density decreases
Solution Approach 1:
The patent transitions from two-dimensional lateral power distribution within device layout cells to three-dimensional power distribution using planes positioned below, between, and above device tiers. This dimensional shift allows power delivery without occupying lateral space in the device layout, thereby reducing area occupation while maintaining or improving integration density.
Solution Approach 2:
The patent introduces inter-tier power distribution planes as intermediary structures that facilitate power delivery between device tiers. These planes act as mediators, providing power distribution pathways that do not require lateral connections within device layout cells, thus reducing the area occupied by power distribution networks.
2Loss of energy
If lateral connections are formed in device layout cells to route vertical power connections, then power distribution is achieved, but resistance increases and power dissipation increases
Solution Approach 1:
The patent replaces high-resistance lateral connections with low-resistance vertical and planar power distribution pathways. By distributing power through planes positioned in three-dimensional space rather than through lateral traces in device layout cells, the patent significantly reduces resistance and associated power dissipation.
Solution Approach 2:
The patent changes the geometric parameters of power distribution structures from thin lateral traces to extended planar structures with larger cross-sectional areas. This parameter change reduces resistance by increasing the conductive path area, thereby reducing power dissipation according to the relationship P = I²R.
3Area of stationary object
If power distribution networks are formed as part of BEOL interconnect network with vertical interconnects, then power delivery to device tiers is achieved, but area occupation increases
Solution Approach 1:
The patent merges power distribution functions across multiple device tiers by implementing continuous power distribution planes that span multiple tiers. This consolidation eliminates the need for separate lateral power distribution networks in each device layout cell, reducing total area occupation while simplifying the overall fabrication process through standardized plane formation.
Data Source
AI summary
Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.