3D Semiconductor Fabrication Using Sacrificial Spacers
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the high cost of processing equipment needed for fine pattern formation, making it challenging to increase memory cell density and reduce production costs.
Innovation Solution
A method for fabricating three-dimensional semiconductor devices involves forming a stacked structure with sacrificial spacers to create recess regions, allowing for the formation of patterned multi-layered structures with varying widths and the integration of conductive patterns, which enhances memory cell density without the need for expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration level is limited by expensive fine pattern forming equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing integration scaling without requiring finer lateral patterning. This dimensional change enables higher density while avoiding the need for expensive fine pattern forming equipment.
Solution Approach 2:
The memory device is divided into multiple discrete layers (first layer, second layer, third layer, fourth layer) that are stacked vertically. Each layer can be formed and patterned separately using standard processing equipment, then assembled into a three-dimensional structure. This segmentation allows complex 3D integration without requiring advanced single-step patterning capabilities.
2Productivity
If three-dimensional semiconductor memory devices are fabricated, then integration level increases, but manufacturing process complexity increases
Solution Approach 1:
Sacrificial spacers are formed on the sidewalls of the stacked structure before the actual memory cell formation. These spacers serve as temporary structures that define the recess regions and protect certain areas during subsequent etching processes. The preliminary formation of these spacers simplifies the overall manufacturing by pre-establishing the three-dimensional geometry needed for high integration.
Solution Approach 2:
The sacrificial spacers act as intermediary structures during fabrication. They are formed conformally on the sidewalls, then selectively removed to create recess regions. These spacers mediate between the stacked layers and the final memory cell structure, enabling precise control of the three-dimensional geometry without requiring complex direct patterning of the memory cells themselves.
3Productivity
If sacrificial spacers are formed to create recess regions, then memory cell density increases, but manufacturing steps increase
Solution Approach 1:
The sacrificial spacers serve multiple functions: they define the recess regions, protect sidewalls during etching, and establish the vertical alignment of memory cells. By forming a single conformal layer that performs these multiple functions, the patent avoids adding excessive manufacturing steps while still achieving high memory cell density through the resulting three-dimensional structure.
Solution Approach 2:
The formation of sacrificial spacers is combined with the stacking process itself. The spacers are formed conformally on the sidewalls of the already-stacked layers, merging the spacer formation step with the structural assembly. This integration of steps reduces the total number of separate manufacturing operations required to achieve high-density three-dimensional memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher memory cell integration and reduced manufacturing costs by using sacrificial spacers to form recess regions and conductive patterns, improving the efficiency and cost-effectiveness of three-dimensional semiconductor device production.
Implementation Method 1
the sacrificial spacer layer may be formed of a material having an etching selectivity with respect to the third layer during the recessing of the exposed sidewall of the third layer
Implementation Method 2
forming a sacrificial spacer layer to conformally cover the stacked structure
Data Source
AI summary
A method of fabricating a three-dimensional semiconductor device includes forming a stacked structure, and the stacked structure includes a first layer, a second layer, a third layer, and a fourth layer sequentially stacked on a substrate. The method also includes forming a sacrificial spacer on a sidewall of the stacked structure such that the sacrificial spacer exposes a sidewall of the third layer, and recessing the exposed sidewall of the third layer thereby forming a recess region between the second and fourth layers.