3D Semiconductor Stacking with Self-Aligned Transistors
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Solution Overview
Problem
Current 3D semiconductor chip technologies face challenges in achieving high-density connections between layers due to the degradation of wiring performance with scaling, misalignment issues during wafer bonding, and the need for high-temperature processing that damages lower wiring layers, limiting connectivity and reliability.
Innovation Solution
The development of a 3D semiconductor device with self-aligned transistors and single crystal silicon channels, where transistors are constructed using ion-cut layer transfer techniques at temperatures below 400°C, enabling precise alignment and high-density connections without degrading existing layers, and the use of junction-less transistors and resistive memory elements in series with transistor selectors for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed using high-temperature processing (>700°C), then transistor performance and density improve, but lower wiring layers are damaged
Solution Approach 1:
The patent divides the transistor construction process into separate temperature stages: low-temperature wiring layer formation (<400°C) followed by high-temperature transistor processing (>700°C) on the same substrate. This segmentation allows each layer to be processed at its optimal temperature without damaging other layers, resolving the contradiction between transistor density improvement and wiring layer integrity.
2Device complexity
If wafer bonding is used for 3D stacking, then layer integration is achieved, but alignment errors occur due to thermal expansion differences and wafer bowing
Solution Approach 1:
The patent performs preliminary alignment mark formation and positioning actions before the actual wafer bonding process. By pre-establishing alignment references and compensating for expected thermal expansion and bowing effects in advance, the system achieves high alignment accuracy despite the inherent challenges of 3D stacking, thus resolving the contradiction between layer integration and alignment precision.
3Adaptability or versatility
If through-silicon via contacts are used for inter-layer connections, then connectivity between layers is established, but contact size must be large and contact density is limited
Solution Approach 1:
The patent introduces an intermediary low-temperature processing layer that facilitates high-density inter-layer connections without requiring large through-silicon via contacts. This intermediary layer acts as a mediator that enables fine-pitch connections and high contact density while maintaining manufacturing feasibility, thus resolving the contradiction between inter-layer connectivity and contact density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the construction of 3D stacked semiconductor chips with reduced alignment errors and high-density connections, enhancing performance and reliability while maintaining the integrity of lower layers, and enabling efficient resistive memory architectures.
Implementation Method 1
transistors are constructed using ion-cut layer transfer techniques at temperatures below 400°C
Data Source
AI summary
A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.