3D Semiconductor Transistor Stack With SiGe Gates for Dense Integration
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the need for expensive equipment to reduce feature sizes, limiting their performance and cost-effectiveness.
Innovation Solution
A three-dimensional semiconductor device with a monolithically integrated circuit structure, featuring a lower substrate with lower transistors, an upper substrate with upper transistors, and conductive lines connecting them, where the upper gate electrode is made of silicon germanium (SiGe) with controlled dopant concentrations, allowing for easier fabrication and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use finer pattern forming technology to increase integration density, then integration density is improved, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar transistor structures to three-dimensional vertically stacked transistor structures. Multiple transistor layers are stacked vertically on a single substrate, enabling significantly higher integration density without requiring further reduction of lateral feature sizes. This dimensional change allows continued scaling of integration density using existing fabrication capabilities.
2Quantity of substance
If feature size is reduced to increase integration density in two-dimensional devices, then integration density is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
By stacking transistor layers vertically, the patent achieves higher integration density while maintaining relatively larger lateral feature sizes. The fabrication process uses standard planar processing techniques repeated for each layer, avoiding the need for extremely complex fine-patterning processes required for continued two-dimensional scaling.
Solution Approach 2:
Multiple transistor layers are nested vertically one on top of another, with each layer containing complete transistor structures. Conductive lines and insulating layers are nested between and around the transistor layers, creating a compact three-dimensional integrated structure that maximizes space utilization.
3Quantity of substance
If three-dimensional stacked structure is implemented to increase integration density, then integration density is improved, but electrical characteristics and performance may deteriorate
Solution Approach 1:
The patent applies different material compositions to different regions of the gate electrodes. Silicon germanium layers with varying germanium concentrations are used in different portions of the gate electrode structure to optimize local electrical characteristics. This allows tailoring of threshold voltages and carrier mobility in specific transistor layers while maintaining overall device performance.
Solution Approach 2:
The patent varies the germanium concentration parameter in the silicon germanium gate electrode materials across different layers and regions. By adjusting this compositional parameter, the electrical characteristics such as threshold voltage and transconductance are optimized for each transistor layer, ensuring reliable performance despite the three-dimensional stacking configuration.
Data Source
AI summary
A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).