3D Semiconductor Stack Segmentation for Integration Density
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in achieving high integration density and reliability due to structural limitations and high fabrication costs, with existing technologies struggling to improve pattern formation processes and maintain electrical characteristics.
Innovation Solution
The design incorporates a stack-structure with alternately stacked gate and insulation patterns, vertical active patterns, and a multi-layered dielectric layer, along with a strapping contact plug and common source region configuration that enhances electrical connectivity and reduces electrical resistance, allowing for improved integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor memory devices are fabricated with conventional structural configurations, then integration density can be increased, but reliability and electrical characteristics deteriorate
Solution Approach 1:
The stack structure is divided into a first portion with constant width and a second portion with reduced width, creating segmented regions that optimize different functional requirements. The first portion maintains structural integrity while the second portion improves electrical characteristics and reliability by reducing resistance and enhancing contact properties.
Solution Approach 2:
Different portions of the stack structure are given different width characteristics tailored to their specific functions. The first portion has uniform width for structural stability, while the second portion has reduced width for improved electrical performance, allowing each region to have optimal local properties for its intended purpose.
2Productivity
If process technology is improved to form finer patterns, then integration density increases, but fabrication costs increase due to high-cost equipment requirements
Solution Approach 1:
The invention transitions from two-dimensional planar structures to three-dimensional stack structures with varying widths in the vertical dimension. This dimensional change allows integration density improvement through vertical stacking rather than requiring ever-smaller lateral feature sizes, avoiding the need for increasingly expensive lithography equipment.
3Reliability
If stack structure width is reduced to improve electrical characteristics, then electrical resistance decreases, but structural stability and manufacturing precision become more difficult to maintain
Solution Approach 1:
The stack structure is segmented into two distinct portions: a first portion with constant width that provides structural stability and ease of manufacturing, and a second portion with reduced width that optimizes electrical characteristics. This segmentation allows each region to be optimized independently for its primary function.
Solution Approach 2:
The structure implements local quality by having different width characteristics in different regions. The first portion maintains larger constant width for structural integrity, while the second portion has reduced width for improved electrical performance, allowing optimal properties in each local region without compromising overall structural stability.
Data Source
AI summary
Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.