3D Semiconductor Device Vertical Stacking Alignment
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Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in interconnect wiring, alignment issues, and the need for high-temperature processing, which affects the reliability and efficiency of three-dimensional stacked integrated circuits.
Innovation Solution
The development of a 3D semiconductor device with multiple layers of single crystal transistors and high-quality oxide isolation, utilizing a layer transfer process that allows for precise alignment and low-temperature bonding, enabling the formation of high-density interconnects and memory cells with reduced parasitic capacitances and resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional Through Silicon Via (TSV) approaches are used for 3D IC interconnection, then electrical connections between bonded wafers can be established, but the TSV density is limited due to large landing pads requirements and large diameter (about one to ten micron) needed to overcome poor wafer to wafer alignment
Solution Approach 1:
The patent transitions from planar 2D interconnection to 3D vertical interconnection by stacking multiple transistor layers vertically. This dimensional change enables significantly higher interconnect density without requiring large landing pads, as the vertical stacking provides additional interconnection pathways through the third dimension.
Solution Approach 2:
The patent segments the interconnection structure into multiple discrete layers (first level, second level, third level, fourth level), each with its own transistors and interconnects. This segmentation allows independent optimization of each layer and enables higher overall density by distributing interconnections across multiple levels rather than relying on a single dense TSV layer.
2Reliability
If high-temperature processing is used to form transistor structures in 3D ICs, then transistor performance can be improved, but the reliability of underlying metallization and low-k intermetal dielectrics deteriorates due to temperature exposure limits below approximately 400° C.
Solution Approach 1:
The patent performs preliminary formation of transistor structures, metallization, and low-k dielectrics on the first wafer before bonding to the second wafer. This preliminary action allows these temperature-sensitive components to be created under controlled conditions, and the subsequent bonding and additional processing on the second wafer can proceed at higher temperatures without affecting the previously formed structures.
Solution Approach 2:
The patent divides the fabrication process into two independent wafer fabrication sequences that are then bonded together. This segmentation allows each wafer to be processed independently at optimal temperatures for its specific structures, with the first wafer containing temperature-sensitive components processed at lower temperatures and the second wafer allowing higher temperature processing for additional transistor layers.
3Productivity
If monolithic 3D integration is used to build transistors on top of interconnected transistor layers, then device density increases, but the allowable temperature exposure is limited to below approximately 400° C. to maintain reliability of high performance lower layer interconnect metallization
Solution Approach 1:
The patent segments the 3D integration into two separately processed wafers that are then bonded together. This allows each wafer to be manufactured independently with full processing flexibility, including high-temperature steps if needed, without constraining the other wafer's processing. The bonded structure achieves high device density while maintaining manufacturing ease.
Solution Approach 2:
The patent uses wafer bonding as an intermediary step that connects two independently processed wafers. This intermediary bonding interface allows each wafer to be processed separately under optimal conditions, then joined together to achieve the final high-density 3D structure without temperature constraints on either side.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.