3D Semiconductor Device Stacking with Thermal Vias
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Solution Overview
Problem
In 3D stacked integrated circuits, the degradation of wire performance with scaling and the challenge of heat removal due to increased power density and thermal resistance hinder the advancement of IC performance and functionality.
Innovation Solution
A method involving the formation of 3D semiconductor devices through epitaxial layer growth, wafer bonding, and thinning, along with the integration of a shielding metal layer and a global power distribution network with enhanced conductivity, to align circuits with less than 200 nm misalignment and facilitate efficient heat removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling is applied to reduce component sizes, then transistor performance and density improve, but wire performance degrades
Solution Approach 1:
The patent transitions from 2D planar integration to 3D stacked architecture, stacking multiple semiconductor layers vertically to reduce interconnect lengths while maintaining high transistor density. This dimensional change allows transistors to be placed closer in the vertical dimension, significantly reducing wire lengths and improving wire performance.
2Loss of time
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but heat removal becomes more difficult due to increased power density and thermal resistance
Solution Approach 1:
The patent segments the heat removal function by introducing dedicated thermal via structures that extend through multiple stacked layers to heat sinks. This segmentation allows heat to be extracted from each layer independently, preventing heat accumulation and improving overall thermal management in the 3D stacked architecture.
Solution Approach 2:
The patent introduces thermal via structures as intermediary heat conduction paths between the stacked semiconductor layers and the heat sinks. These thermal vias act as mediators to efficiently transfer heat from high-power-density regions to cooling structures, addressing the thermal management challenge.
3Reliability
If epitaxial layer growth is used to form semiconductor layers, then single crystalline structure is achieved, but high temperatures are typically required
Solution Approach 1:
The patent changes the processing temperature parameter by implementing low-temperature epitaxial growth techniques, enabling the formation of high-quality single crystalline semiconductor layers at reduced temperatures that are compatible with existing device structures and materials.
4Productivity
If wafer bonding is performed to stack layers, then 3D integration is achieved, but alignment precision must be maintained at less than 200 nm
Solution Approach 1:
The patent implements preliminary alignment mark formation and precise positioning procedures before the wafer bonding process. Alignment marks are pre-formed on the wafers, and precise positioning mechanisms are employed during bonding to ensure sub-200 nm alignment accuracy between stacked layers, enabling high-density 3D integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of defect-free single crystalline semiconductor layers at low temperatures, improves wire performance, and enhances heat removal efficiency by reducing thermal resistance, thereby addressing the limitations of existing 3D IC technologies.
Implementation Method 1
performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer comprising non silicon atoms
Implementation Method 2
transferred and then bonding the second wafer on top of the first wafer
Data Source
AI summary
A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than thirty microns, where the bonding includes oxide to oxide bonds, where the bonding includes metal to metal bonds, and where at least one of the metal to metal bond structures has a pitch of less than 1 micron from another of the metal to metal bond structures.