3D Semiconductor Devices With String Selection Structure
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Solution Overview
Problem
The economic limitation of increasing integration in two-dimensional semiconductor memory devices due to the high cost of equipment required for forming fine patterns, which hinders the development of high-performance, low-cost devices.
Innovation Solution
The development of three-dimensional semiconductor devices with a string selection structure for selective connections between active patterns and bit lines, including a common source structure and memory structure on a substrate, utilizing semiconductor materials with varying conductivity types and impurity concentrations to control energy band structures and depletion regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory devices use fine pattern formation techniques to increase integration, then integration density improves, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple layers of memory cells are stacked vertically with interconnection lines extending through the stack, enabling higher integration density without requiring finer lateral patterning. This vertical dimension adds capacity while using conventional fabrication capabilities.
2Manufacturing precision
If three-dimensional memory devices are developed to overcome integration limitations, then integration density improves, but device complexity increases
Solution Approach 1:
The three-dimensional memory device is segmented into multiple distinct layers including memory cell layers, string selection structure layers, and common source structure layers. Each layer performs a specific function and can be independently controlled through selective voltage application to respective control gates, simplifying the overall operation despite the vertical complexity.
Solution Approach 2:
The control gates in the vertical memory structure serve multiple functions: they enable selective access to different memory cell layers, control current flow through memory strings, and facilitate various memory operations (read, program, erase) through different voltage combinations applied to the same physical structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and selective connections between memory elements, allowing for higher integration density and performance while reducing costs by leveraging the vertical arrangement of memory cells and interconnection lines.
Implementation Method 1
layer-selection patterns sequentially stacked to control an energy band structure of the end-portions of the active patterns located at the same level
Implementation Method 2
The string selection structure is configured to select a plurality of the memory elements at a given level relative to the top surface of the substrate, while simultaneously refraining from selecting other memory elements that overlie or underlie the plurality of memory elements at the given level
Data Source
AI summary
Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.