3D Semiconductor Devices with Substrate Voids
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the expense and complexity of fine pattern forming technologies, which restricts their ability to increase memory density effectively.
Innovation Solution
A three-dimensional semiconductor device design featuring gate electrodes stacked on a substrate with a channel structure passing through the gate electrodes and a void in the substrate, allowing for improved electrical characteristics and reliability by optimizing the placement and structure of semiconductor patterns and residue layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration is limited by the area occupied by unit memory cell and fine pattern forming technology cost
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, with gate electrodes and channel structures arranged in three dimensions. This dimensional change allows memory density to increase without requiring proportionally smaller planar features, thereby overcoming the limitations of fine pattern forming technology while maintaining manufacturing feasibility.
2Quantity of substance
If three-dimensional semiconductor devices with vertically stacked gate electrodes are used, then memory density increases, but electrical characteristics and reliability may deteriorate due to process variations
Solution Approach 1:
The patent employs selective etching processes with controlled etch rates to form voids of specific depths in different regions. By adjusting etching parameters (time, power, gas flow), the void depth is precisely controlled to compensate for variations in gate electrode and insulating layer thicknesses. This parameter control ensures uniform channel lengths and electrical characteristics across all memory cells, maintaining reliability while achieving high density.
Solution Approach 2:
The patent incorporates a feedback mechanism where the void formation process is controlled based on measured or predetermined dimensions of the stacked structures. The etching process automatically adjusts to create voids that compensate for manufacturing variations, ensuring that the final channel structures have uniform electrical properties. This self-correcting approach maintains reliability despite inherent process variations.
3Reliability
If channel structure passes through substrate to improve electrical characteristics, then manufacturing complexity increases due to through-hole formation and residue layer management
Solution Approach 1:
The patent extracts or removes substrate material to form through-holes that allow channel structures to pass through the substrate. This extraction creates vertical pathways for electrical connection while removing interfering substrate material. The process selectively removes material only where needed, managing complexity by focusing modifications only in critical regions rather than modifying the entire substrate.
Solution Approach 2:
The patent introduces voids as intermediary structures between the channel structures and the substrate. These voids serve as mediating elements that facilitate electrical connection while managing the interface between different structural components. The voids act as buffers that accommodate manufacturing variations and ensure reliable electrical characteristics without requiring perfectly precise direct connections.
Data Source
AI summary
A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.