3D Semiconductor Devices Terraced Contact Structures
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Solution Overview
Problem
The challenge in manufacturing three-dimensional semiconductor devices is the high cost and limited integration capacity of two-dimensional devices, which restricts the increase in integration density due to the need for expensive equipment to form fine patterns, and there is a need for a cost-effective method to achieve reliable product characteristics in mass production.
Innovation Solution
A method involving the formation of a substrate with wiring and contact regions, a thin film structure with alternating sacrificial layers and insulating layers, and the removal of these layers to create recess regions for filling with conductive material, allowing for the formation of terraced structures and vertical contact patterns that enhance integration density without requiring expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional planar semiconductor devices are used to increase integration density, then manufacturing cost increases due to expensive equipment requirements, but three-dimensional structures are needed to achieve cost-effective high integration
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional stacked structures by forming multiple layers of memory cells vertically above each other. This dimensional change allows integration density to increase without proportionally increasing manufacturing complexity, as the same fabrication processes are extended into the vertical dimension rather than requiring entirely new equipment for fine pattern formation.
Solution Approach 2:
The three-dimensional structure is segmented into multiple discrete layers (first memory cell layer, second memory cell layer, etc.) separated by inter-layer insulating layers. Each layer can be formed using standard planar fabrication techniques, and the segmentation allows independent optimization of each layer while achieving high overall integration through vertical stacking.
2Quantity of substance
If three-dimensional semiconductor devices are manufactured with complex structures, then integration density increases, but manufacturing reliability decreases due to process complexity
Solution Approach 1:
Sacrificial layers are formed in advance before the final memory cell structures are completed. These sacrificial layers serve as temporary placeholders that define the three-dimensional geometry during fabrication. By performing the complex 3D structuring action preliminarily with sacrificial material, the actual functional layers can be deposited conformally without requiring complex real-time patterning, thus maintaining reliability.
Solution Approach 2:
Sacrificial layers act as intermediary elements that facilitate the formation of complex three-dimensional structures. These temporary layers mediate between the simple planar fabrication processes and the desired complex 3D geometry. After the functional memory cell layers are formed conformally on the sacrificial structures, the sacrificial layers are removed and replaced with conductive materials to complete the interconnect structure.
3Adaptability or versatility
If sacrificial layers and complex patterning are used to form three-dimensional structures, then manufacturing flexibility increases, but process steps increase leading to higher costs
Solution Approach 1:
Multiple process functions are merged into single steps. For example, the formation of inter-layer insulating layers and conformal deposition of memory cell layers are combined in sequential operations that leverage the same equipment and process conditions. The sacrificial layer removal and conductive material filling are merged into a single etch-and-fill cycle, reducing the total number of discrete process steps while maintaining manufacturing flexibility.
Solution Approach 2:
The sacrificial layer structure serves multiple functions simultaneously: it defines the three-dimensional geometry, provides a template for conformal deposition of functional layers, and acts as a placeholder for future interconnect formation. This multi-functionality reduces the need for separate dedicated structures for each purpose, thereby reducing overall process complexity while maintaining adaptability.
Data Source
AI summary
A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.