3D Semiconductor Thermal Via Heat Conduction Paths
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Solution Overview
Problem
Three-dimensional integrated circuits (3D-ICs) face significant challenges in heat removal due to increased power density and high thermal resistance, particularly in stacked configurations where heat transfer from semiconductor layers to heat sinks is hindered by the poor conductivity of wiring dielectric regions and shallow trench isolation (STI) materials.
Innovation Solution
The implementation of thermal conducting paths, such as thermally conductive shallow trench isolation (STI) regions, pre-metal dielectric regions, etch stop layers, and thermal contacts, along with heat spreaders and thermally conductive materials, is used to enhance heat transfer and reduce thermal resistance within the 3D-IC structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple layers of transistors are stacked in 3D configuration, then transistor density and performance are improved, but heat removal capability deteriorates due to increased power density and high thermal resistance
Solution Approach 1:
The patent introduces vertical thermal conduction paths through the stacked layers, transitioning from traditional planar heat removal to three-dimensional thermal management. Thermal vias and conductive paths extend heat transfer in the vertical dimension, allowing heat to escape from upper transistor layers directly to heat sinks on the substrate or opposite side, thereby resolving the heat removal bottleneck in 3D stacked configurations
Solution Approach 2:
The patent employs thermal vias filled with high thermal conductivity materials as intermediary structures between the transistor layers and heat sinks. These thermal vias act as mediators that bridge the thermal gap created by stacking, providing dedicated heat conduction pathways that bypass the thermally resistive wiring dielectric and STI materials, thus enabling effective heat removal from densely stacked transistors
2Reliability
If wiring dielectric regions and STI materials are used for isolation, then electrical insulation is improved, but thermal conduction capability deteriorates
Solution Approach 1:
The patent applies different material properties to different spatial locations: wiring dielectric and STI materials provide electrical insulation in the lateral directions, while thermal via materials provide thermal conduction in the vertical direction. This local differentiation of material qualities allows the structure to simultaneously achieve electrical isolation and thermal management, with each region optimized for its specific function
Solution Approach 2:
The patent uses composite material structures where thermal vias filled with high thermal conductivity materials (such as copper or diamond) are embedded within the electrical insulation matrix of wiring dielectric and STI materials. This composite approach creates a multi-functional structure that combines electrical insulation properties of the dielectric materials with thermal conduction properties of the via materials, resolving the contradiction between electrical isolation and heat removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These measures effectively reduce thermal resistance and improve heat removal capabilities, allowing for the maintenance of desirable temperature levels in 3D-ICs, even in stacked configurations, by providing efficient conduction paths for heat from transistors to the heat removal apparatus.
Implementation Method 1
at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device
Data Source
AI summary
An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.