3D Semiconductor Device Structure for Small-Area, High-Current Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving miniaturization, high on-state current, favorable electrical characteristics, low power consumption, and high reliability, while also requiring high-resolution display capabilities and efficient manufacturing processes.
Innovation Solution
A semiconductor device design incorporating specific layer configurations, including a semiconductor layer, conductive layers, and insulating layers, with a back gate electrode structure to stabilize the channel potential and enable a small channel length, thereby enhancing electrical performance and reducing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the transistor size is reduced to achieve miniaturization, then the pixel size can be smaller and higher resolution can be achieved, but the on-state current decreases and electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from a planar transistor structure to a three-dimensional structure by forming the semiconductor layer to surround the gate electrode in a U-shape configuration. This vertical integration allows the transistor to achieve higher effective channel width without increasing planar area, thereby maintaining or improving on-state current while reducing the footprint area occupied by the transistor.
Solution Approach 2:
The semiconductor layer is formed to wrap around the gate electrode, creating a nested configuration where the gate is embedded within the semiconductor structure. This nesting approach maximizes the interaction between the gate and semiconductor material within a compact volume, enhancing electrical control and current flow without requiring additional lateral space.
2Length of moving object
If the channel length is reduced to miniaturize the transistor, then the device area is reduced, but the electrical characteristics and reliability deteriorate
Solution Approach 1:
The patent extends the channel region vertically by forming the semiconductor layer to wrap around the gate electrode in three dimensions. This creates an effective channel length that includes both lateral and vertical components, allowing the transistor to achieve sufficient channel length for proper electrical characteristics while maintaining a compact planar footprint.
3Ease of manufacture
If conventional planar transistor structures are used, then manufacturing is simpler, but the transistor occupies larger area and cannot achieve high resolution
Solution Approach 1:
The manufacturing process is segmented into sequential deposition and etching steps that build the three-dimensional structure layer by layer. The gate electrode is formed first, followed by semiconductor layer deposition that completely covers it, then selective etching creates the wrapping configuration. This segmented approach maintains manufacturing simplicity while achieving the compact three-dimensional structure.
Data Source
AI summary
A semiconductor device that occupies a small area is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first conductive layer with the first insulating layer therebetween. The second insulating layer covers the top surface and a side surface of the second conductive layer. The third conductive layer is positioned over the second insulating layer. The semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second insulating layer, and the third conductive layer. The third insulating layer is positioned over the semiconductor layer. The fourth conductive layer is positioned over the semiconductor layer with the third insulating layer therebetween.