3D Semiconductor Device With Tungsten Vias For High-Density Interconnects
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Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in interconnect wiring, wafer alignment, and processing temperatures, leading to inefficiencies in device scaling and increased costs.
Innovation Solution
The development of a 3D semiconductor device with a layered structure using single crystal silicon transistors and tungsten vias of specific diameters, enabling high-density interconnects and low-temperature processing to overcome these limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 3D IC technologies are used with standard interconnect wiring, then device scaling can be achieved, but transistor performance and density are limited due to interconnect wiring limitations
Solution Approach 1:
The patent transitions from planar 2D interconnect wiring to three-dimensional vertical interconnect structures. Through-silicon vias (TSVs) enable vertical connections between stacked device layers, adding the z-dimension to interconnect topology. This dimensional change reduces lateral wiring congestion and enables higher device density while maintaining signal integrity and transistor performance.
Solution Approach 2:
The patent segments the interconnect system into multiple independent metal layers with different functions. Signal lines, power lines, and ground lines are separated into distinct metal layers, allowing independent optimization of each interconnect type. This segmentation reduces electromagnetic interference and enables higher frequency operation, improving both transistor performance and overall device density.
2Manufacturing precision
If wafer alignment is used in conventional 3D IC fabrication, then layer stacking is achieved, but alignment limitations reduce manufacturing precision and increase costs
Solution Approach 1:
The patent incorporates alignment marks and registration features during the initial wafer fabrication stage, before stacking operations. These pre-formed features serve as precise registration targets during subsequent bonding and stacking processes. By performing alignment preparation in advance rather than during stacking, the patent achieves sub-micron alignment precision while reducing the complexity and cost of alignment systems required during assembly.
Solution Approach 2:
The patent introduces intermediary alignment layers and registration structures that mediate between different wafer layers during stacking. These intermediary features provide mechanical and optical reference points that enable precise alignment without requiring complex real-time measurement systems. The alignment layers act as intermediaries that translate design coordinates to physical positions, achieving high precision at lower cost.
3Reliability
If high processing temperatures are used in conventional 3D IC fabrication, then material properties are achieved, but processing temperatures increase manufacturing complexity and reduce yield
Solution Approach 1:
The patent modifies processing temperature parameters by introducing intermediate annealing steps at lower temperatures between high-temperature processing stages. Instead of continuously high temperatures, the process uses temperature cycling with intermediate low-temperature annealing to relieve thermal stress and prevent defect formation. This parameter modulation maintains necessary material properties while reducing cumulative thermal damage and improving overall fabrication yield.
4Productivity
If standard via diameters are used in conventional 3D ICs, then interconnect formation is achieved, but interconnect density is limited
Solution Approach 1:
The patent implements local quality variations in via formation by using different via diameters for different functional regions. Critical signal vias use smaller diameters for higher precision and lower capacitance, while power and ground vias use larger diameters for higher current capacity. This localized optimization of via dimensions allows the patent to achieve high overall interconnect density while maintaining the manufacturing precision required for each specific via type.
Data Source
AI summary
A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.