3D Semiconductor Device With Vertical Buffer For Gate Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration and reliability due to limitations in the stacking and spacing of gate electrodes, which affect the performance and durability of three-dimensional semiconductor structures.
Innovation Solution
A three-dimensional semiconductor device design featuring stacked gate electrodes with varying widths and insulating layers, including a vertical structure with a buffer portion to prevent defects, and separation structures that enhance integration and reliability by allowing for precise control of electrode spacing and material selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate electrodes are stacked closely to increase integration density, then device integration improves, but manufacturing precision and reliability deteriorate due to spacing control difficulties
Solution Approach 1:
A buffer portion is introduced between the lower gate electrode group and upper gate electrode group, serving as an intermediary structure. This buffer portion includes a buffer hole extending through the lower gate electrode group and filled with conductive material, providing a controlled transition zone that facilitates precise spacing and alignment between the two groups while maintaining high integration density
Solution Approach 2:
The gate electrode structure is segmented into distinct lower and upper groups with a buffer portion in between. This segmentation allows independent optimization of each group's characteristics and spacing, enabling better control over manufacturing precision while achieving high integration through vertical stacking
2Productivity
If gate electrodes are stacked in vertical direction to improve integration, then device complexity increases, but reliability deteriorates due to defect propagation risks
Solution Approach 1:
The buffer portion acts as a cushioning structure positioned beforehand between the lower and upper gate electrode groups. It includes insulating layers and conductive fill material that absorb and isolate potential defects, preventing defect propagation from one group to another while maintaining the vertical stacked configuration for high integration
3Ease of manufacture
If uniform width is used for all vertical structures to simplify manufacturing, then ease of manufacture improves, but device performance deteriorates due to lack of optimized electrical characteristics
Solution Approach 1:
Different vertical structures are assigned different widths according to their specific functional requirements. The buffer portion, gate electrodes, and connection structures each have optimized width dimensions tailored to their electrical and mechanical needs, achieving superior device performance while the manufacturing process remains manageable through localized rather than uniform design
Data Source
AI summary
A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.