3D Semiconductor Memory Structure for Vertical Cell Integration
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in increasing memory capacity due to their inherent two-dimensional structure, which restricts the degree of integration and thus the capacity of memory cells.
Innovation Solution
A three-dimensional semiconductor memory device is proposed, featuring a substrate with bit lines extending vertically and transistor bodies with monocrystalline channel layers, gate dielectric layers, and cell capacitors, allowing for increased memory capacity by stacking memory cells in a vertical direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional semiconductor memory device structure is used, then manufacturing process is simple, but degree of integration and memory capacity are limited
Solution Approach 1:
The patent transitions from a two-dimensional memory cell layout to a three-dimensional structure by forming transistor bodies that extend vertically from the substrate. Multiple gate electrode layers are stacked in the vertical direction, and bit lines extend vertically to connect to transistor bodies at different heights, enabling increased memory capacity without proportionally increasing the substrate area.
2Device complexity
If two-dimensional semiconductor memory device structure is used, then device structure is simple, but degree of integration is limited
Solution Approach 1:
The patent employs vertical stacking of multiple gate electrode layers (first, second, third, and fourth gate electrode layers) and forms transistor bodies that extend in the vertical direction. This three-dimensional arrangement increases the number of memory cells per unit area, thereby improving the degree of integration while maintaining structural clarity through systematic layering.
3Quantity of substance
If vertical stacking of memory cells is implemented, then memory capacity increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into distinct functional segments: substrate layer, transistor bodies with source-drain regions, multiple gate electrode layers, bit lines, and cell capacitors. Each segment is formed through separate processing steps but integrates systematically to create the overall three-dimensional structure, making the complex manufacturing process more manageable and systematic.
Solution Approach 2:
The patent implements vertical stacking of gate electrode layers and transistor bodies, with bit lines extending vertically to connect to source-drain regions at different heights. This three-dimensional configuration increases memory capacity by utilizing the vertical dimension for cell arrangement, thereby improving integration density despite increased manufacturing complexity.
Data Source
AI summary
A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.