3D Semiconductor Device Vertical Channel Integration
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Solution Overview
Problem
Two-dimensional memory semiconductor devices face limitations in economic integration due to expensive equipment for forming fine patterns, necessitating the development of three-dimensional memory devices with increased integration capabilities.
Innovation Solution
A three-dimensional semiconductor device is designed with a substrate featuring bit lines, a common source line, and channel pipes with columnar and coupling portions, along with a gate structure including word lines, string selection lines, and ground selection lines, allowing for increased integration and simplified fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory semiconductor devices use fine pattern formation techniques to increase integration, then integration capability is improved, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Memory cells are arranged in multiple layers along the vertical direction, with bit lines, source lines, and channel structures extending through multiple levels. This dimensional change enables significantly higher integration density without requiring proportionally more expensive fine-patterning equipment, as the vertical stacking utilizes the third dimension for capacity expansion.
2Productivity
If three-dimensional memory devices increase the number of bit lines to increase page depth, then data processing capacity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple bit lines (first bit lines and second bit lines) into a unified three-dimensional architecture where they intersect and interact through shared channel structures and source lines. This merging allows the device to achieve increased page depth and data processing capacity while managing complexity through integrated design, where the interaction between bit lines, channel structures, and source lines creates a coordinated system rather than separate independent components.
Data Source
AI summary
A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.