3D Semiconductor Device Vertical Stacking for Transistor Density
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to overcome scaling limitations in two-dimensional (2D) circuits by transitioning to three-dimensional (3D) integration, where transistors are stacked vertically to increase transistor density in volume rather than area, which is particularly difficult for logic chips like CPUs and GPUs.
Innovation Solution
The solution involves building vertically stacked semiconductor devices with a stack of layers including source, gate, and drain layers, and forming vertical channel structures that define an inner axis transverse to the main surface, with vertical contact structures configured to electrically connect to these layers, allowing for 360-degree access and reduced mask steps through a process that includes epitaxial growth and directional etching to form interconnection structures between stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are arranged in one plane (2D circuits), then fabrication processes are simpler, but transistor density per unit area is limited
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangement to three-dimensional vertical stacking. Multiple transistor layers are stacked vertically with each layer containing source, gate, and drain regions arranged in different planes, enabling increased transistor density in the vertical dimension while maintaining manageable fabrication processes through sequential formation of each layer
2Quantity of substance
If transistors are stacked vertically (3D circuits), then transistor density in volume increases, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into sequential steps for forming each transistor layer independently. Each layer's source, gate, and drain regions are formed in separate fabrication steps, allowing complex 3D structures to be built from simpler 2D components. This segmentation reduces overall fabrication complexity by breaking down the 3D stacking process into manageable sequential operations
Solution Approach 2:
The patent forms the source and drain regions of each transistor layer before forming the gate region of that same layer. This preliminary action simplifies subsequent processing steps and enables systematic vertical stacking by establishing a consistent formation sequence that can be repeated for multiple layers without increasing overall process complexity
3Reliability
If vertical contact structures are formed to connect terminal layers, then connectivity between stacked transistors is improved, but manufacturing complexity increases
Solution Approach 1:
The vertical contact structures serve multiple functions: they provide electrical connectivity between terminal layers of adjacent transistor stacks, act as alignment references for subsequent processing steps, and enable both source/drain and gate terminal access through standardized formation procedures. This multi-functionality reduces overall manufacturing complexity by consolidating multiple requirements into unified structural elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances vertical routing density and transistor density in volume, enabling compact 360-degree wiring connections and reducing the number of mask steps required, facilitating the transition from 2D to 3D stacking while improving connectivity between stacked transistors.
Implementation Method 1
The vertical channel structure extends from a source region, through a gate region, to a drain region
Implementation Method 2
The vertical channel structures are separated from each other by a dielectric material
Data Source
AI summary
A semiconductor device includes a stack of layers, a vertical channel structure and vertical contact structures. The stack of layers defines a sidewall surface and includes terminal layers which include source, gate and drain layers. The vertical channel structure defines an inner axis that is substantially transverse to a main surface of the stack of layers. The vertical contact structures are each configured to electrically connect to a respective terminal layer. At least two vertical contact structures are in different radial positions relative to the inner axis.