3D Semiconductor Device Vertical Horizontal Channel Connectivity
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration density due to the high cost and complexity of forming fine patterns, leading to a need for three-dimensional semiconductor devices that can enhance reliability and integration density.
Innovation Solution
A three-dimensional semiconductor device is designed with a stack structure featuring vertically stacked electrodes, channel structures, and conductive plugs, where first and second vertical channels are connected by a first horizontal channel, and second horizontal channels are in contact with the sidewalls of the first horizontal channel, enabling improved connectivity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor devices are used, then manufacturing processes are simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked devices. Multiple memory cells are stacked vertically along the third dimension, with electrodes and channel structures arranged in multiple layers. This dimensional change enables significantly higher integration density while maintaining manufacturing feasibility through established thin-film deposition and etching processes.
2Quantity of substance
If three-dimensional vertically stacked structures are implemented, then integration density is improved, but device complexity increases
Solution Approach 1:
The three-dimensional structure is segmented into repeating modular units, each consisting of a stack of electrodes and channel structures. Multiple memory cells are organized as identical or similar stacked modules arranged in arrays. This segmentation allows complex 3D structures to be manufactured using repeated deposition and etching cycles, reducing overall device complexity through standardization.
Solution Approach 2:
The patent employs nested structures where channel structures are positioned within and between electrode stacks. Multiple layers of electrodes and channels are nested vertically, with each layer containing smaller structural elements within the broader stack architecture. This nesting enables high integration density by efficiently utilizing vertical space while maintaining organized, manufacturable structures.
3Quantity of substance
If fine patterns are formed to increase integration density, then manufacturing precision requirements increase, but manufacturing cost increases
Solution Approach 1:
Instead of increasing integration density through finer lateral patterning in two dimensions, the patent achieves high density by stacking structures vertically in the third dimension. The lateral pattern sizes can remain relatively large and easy to manufacture, while the vertical stacking provides the integration density multiplication. This approach reduces manufacturing precision requirements compared to achieving the same density through lateral scaling.
Data Source
AI summary
A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.