3D Semiconductor Layer Structure for Dense Vertical Interconnects
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing, particularly for custom products targeting smaller volume and less diverse markets, and the limitations of current 3D IC technologies due to large Through-Silicon-Via (TSV) size, which restricts vertical connectivity and increases development costs.
Innovation Solution
The development of multilayer or Three Dimensional Integrated Circuit (3D IC) devices using single crystal transistors with oxide-to-oxide bonding and hybrid bonds, along with advanced layer transfer techniques such as SmartCut and wafer bonding, to reduce lithography steps and enhance vertical connectivity, allowing for more efficient and cost-effective construction of complex ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) technology is used for 3D IC construction, then vertical connectivity is achieved, but TSV size is large which restricts vertical connectivity and increases development costs
Solution Approach 1:
The patent segments the interconnection structure into multiple components: shallow trenches filled with conductive material for vertical connectivity, and bond wires for horizontal connectivity. This segmentation allows each component to be optimized independently, achieving good vertical connectivity without requiring large TSV structures.
Solution Approach 2:
The patent transitions from a planar 2D interconnection architecture to a three-dimensional architecture by introducing shallow trenches that extend vertically into the semiconductor substrate. This dimensional change enables vertical signal routing without requiring large-diameter through-silicon vias, thereby improving vertical connectivity while reducing structure size.
2Ease of manufacture
If mask set cost is reduced for custom products, then development cost decreases, but manufacturing precision and device density improvement are limited
Solution Approach 1:
The patent employs standard lithography masks that can be used across multiple product generations and custom designs. The shallow trench interconnection structure and bonding methodology are universally applicable to different device configurations, allowing the same mask set to serve both high-volume production and custom product development, thereby reducing development costs without sacrificing manufacturing precision.
Solution Approach 2:
The patent uses photolithography to create precise patterns in the semiconductor substrate and mask layers. By using standard mask sets with proven patterning capabilities, the process achieves high manufacturing precision for critical dimensions while avoiding the need for expensive custom mask sets, as the standard masks can be reused across multiple products.
3Device complexity
If lithography steps are reduced in 3D IC construction, then manufacturing complexity and cost decrease, but alignment precision between layers may be compromised
Solution Approach 1:
The patent incorporates alignment marks and registration features directly into the substrate and mask layers during earlier processing steps. These preliminary features enable precise alignment between subsequent lithography steps without requiring additional alignment operations, thereby reducing overall manufacturing complexity while maintaining high alignment precision between stacked layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides an order of magnitude improvement in vertical connectivity, reduces development costs, and enhances the yield and reliability of complex 3D ICs, making them more viable for future generations of ICs.
Implementation Method 1
first bond regions comprising first oxide to oxide bonds, wherein said first bond regions are disposed between said first level and said second level
Implementation Method 2
advanced layer transfer techniques such as SmartCut and wafer bonding
Implementation Method 3
hybrid bonds
Data Source
AI summary
A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.