3D Semiconductor Fabrication via Vertical Stacking and Selective Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices approach single-digit nanometer fabrication nodes, traditional 2D transistor scaling faces challenges due to manufacturing variability and electrostatic device limitations, necessitating a transition to 3D integration for increased transistor density.
Innovation Solution
The method involves forming a multilayer stack with gate dielectric layers, transition dielectric layers, and source/drain dielectric layers on a substrate, creating vertical channels and replacing materials to form 3D semiconductor devices, enabling the stacking of transistors and increasing transistor density through thermal bonding of nanoplane dielectric layer stacks on separate substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D transistor scaling is continued, then transistor density per unit area increases, but manufacturing variability and electrostatic device limitations worsen
Solution Approach 1:
The patent transitions from 2D planar transistor scaling to 3D vertical stacking, where multiple transistor layers are stacked vertically on the substrate. This dimensional change allows continued density improvement without further scaling individual transistors in the planar direction, thereby avoiding the electrostatic and manufacturing variability limitations that plague single-digit nanometer 2D nodes.
2Quantity of substance
If 3D integration is implemented, then transistor density in volume increases, but device complexity and fabrication process difficulty increase
Solution Approach 1:
The 3D integrated structure is divided into multiple discrete transistor layers stacked vertically, with each layer containing complete transistor devices. This segmentation allows independent formation and processing of each layer, making the complex 3D structure manageable through repeated application of standard 2D fabrication processes across multiple layers.
Solution Approach 2:
Multiple complete transistor layers are nested vertically one on top of another, with each layer containing transistors that are electrically isolated but structurally integrated. The nested arrangement allows high-density volume utilization while maintaining the functional independence of each transistor layer through dielectric isolation and selective interconnection.
3Length of moving object
If contacted gate pitch is reduced for scaling, then transistor size decreases, but manufacturing variability and electrostatic limitations worsen
Solution Approach 1:
Instead of further reducing gate pitch in the lateral direction, the patent stacks multiple transistor layers vertically, each with their own gate structures. This vertical stacking provides continued scaling of device density without requiring further reduction of the already-critically-scaled gate pitch, thereby maintaining manufacturability and electrostatic performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density in volume, overcoming scaling limitations and enabling continued semiconductor roadmap advancements by facilitating the integration of 3D semiconductor circuits with increased packing density and performance.
Implementation Method 1
etching the transition dielectric layer to uncover a portion of the first channel and the second channel that interface at the transition dielectric layer
Implementation Method 2
oxidizing the uncovered portion of the first channel and the second channel to form an isolation region
Implementation Method 3
thermal bonding of separate nanoplane dielectric layer stacks on separate substrates to form a combined dielectric layer stack
Data Source
AI summary
Aspects of the present disclosure provide a method for fabricating a 3D semiconductor apparatus. The method can include forming a multilayer stack including a plurality of dielectric layers. The dielectric layers can include three or four dielectric materials that can be etched selectively with respect to one another. The method can also include forming opening(s) in the multilayer stack, and filling the opening(s) with first and second channel materials to form first and second channels that interface at a transition dielectric layer the multilayer stack. The method can also include removing second and first source/drain (S/D) dielectric layers of the multilayer stack and replacing with second and first S/D materials to form second and first S/D regions, respectively. The method can also include removing gate dielectric layers of the multilayer stack and replacing with a gate material to form gate regions of the 3D semiconductor apparatus.