3D Semiconductor Device Vertical Stacking Integration
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Solution Overview
Problem
The high cost of increasing integration in two-dimensional semiconductor devices limits their performance and affordability, as finer pattern formation requires expensive equipment, and three-dimensional semiconductor devices are sought to overcome these limitations.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked electrodes, interlayered insulating layers, support patterns, and electrode separation structures, which enhance reliability and integration by allowing for increased spacing and efficient electrical connections without the need for expensive processing equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use finer pattern formation to increase integration, then integration density is improved, but manufacturing cost increases due to expensive processing equipment
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertically stacked structures. Multiple electrodes and insulating layers are stacked in the vertical direction to form memory cells, allowing integration density to increase without requiring finer lateral patterning. This dimensional change enables higher integration while avoiding the need for expensive fine-patterning equipment.
2Reliability
If three-dimensional semiconductor devices increase spacing between components for reliability, then device reliability is improved, but area occupied increases
Solution Approach 1:
The patent utilizes the vertical dimension to accommodate increased spacing between components. By stacking electrodes and insulating layers vertically, the device achieves greater separation distances between adjacent elements without increasing the lateral footprint. This allows reliability improvements through increased spacing while maintaining compact area occupation.
Solution Approach 2:
The patent employs nested structures where multiple electrodes and insulating layers are stacked one within another in the vertical direction. This nesting approach allows components to be arranged in three dimensions, enabling increased spacing between adjacent elements while maintaining a compact overall structure that does not occupy excessive lateral area.
Data Source
AI summary
A three-dimensional semiconductor device is disclosed. The device may include first and second stacks separated from each other in a first direction, with each of the stacks including electrodes vertically stacked on a substrate. The device may also include vertical channel structures that penetrate the electrodes and are connected to the substrate, an interlayered insulating layer on top surfaces of the vertical channel structures, and a support pattern located between opposite sidewalls of the first and second stacks, in the interlayered insulating layer. A bottom surface of the support pattern may be positioned at a higher level than a top surface of an uppermost electrode of the electrodes.