3D Semiconductor Via Alignment and Density
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Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in Through-Silicon Via (TSV) density, alignment issues, and the cost of Silicon On Insulator (SOI) wafers, as well as difficulties in maintaining reliable low-temperature processing for high-performance transistors.
Innovation Solution
The development of a 3D semiconductor device with a layered structure that includes single crystal silicon layers, transistors with single crystal channels, and metal interconnections, where vias are formed through the silicon layer to connect transistors with high precision and alignment, enabling efficient interconnects and reducing the need for high-temperature processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through-Silicon Via (TSV) technology is used to connect stacked chips, then 3D integration is achieved, but TSV density is limited due to large landing pad requirements and alignment difficulties
Solution Approach 1:
The patent applies preliminary action by forming vias and filling them with conductive material through the transferred layer before the actual wafer bonding occurs. This preliminary via formation allows for precise alignment to be established in advance, and the via structures serve as alignment references during bonding, thereby overcoming the alignment precision limitations that would otherwise constrain interconnection density.
2Productivity
If Silicon On Insulator (SOI) wafers are used to reduce TSV diameter, then TSV density improves, but production cost increases
Solution Approach 1:
The patent employs a transferred layer that can be selectively removed after serving its purpose as a temporary substrate for via formation. This disposable transferred layer approach allows via creation without requiring expensive SOI wafers, as the transferred layer is discarded after the via structures are formed and transferred to the final substrate, thereby reducing production costs while maintaining high TSV density.
3Reliability
If low-temperature processing is used to maintain reliability of underlying metallization, then device reliability is improved, but transistor performance suffers
Solution Approach 1:
The patent segments the processing temperatures for different functional requirements: low-temperature processing is used for forming and filling vias through the transferred layer to protect underlying metallization, while high-temperature processing is applied afterward to the final structure to activate dopants and form high-performance transistors. This temporal and functional segmentation of temperature regimes allows both metallization reliability and transistor performance to be optimized.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the transistors includes a four sided gate.