3D Sense Amplifier Placement for Memory Routing
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Solution Overview
Problem
Three-dimensional memory devices face challenges with signal loss and timing delays due to the long routing distances between memory cells and sense amplifiers, leading to increased complexity and size of memory logic circuits, which are exacerbated by the use of vertical transistors.
Innovation Solution
The placement of 3D sense amplifiers at the same level as vertical transistors reduces routing distances, improving performance, reliability, and efficiency by using semiconductor layers disposed on conductive layers, with options for gate contact formation and transistor arrangements that allow for shared gate contacts and interchanged roles of top and bottom doping regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sense amplifiers are placed at a different level from memory cells (conventional arrangement), then manufacturing precision can be optimized, but routing distance increases causing signal loss and timing delays
Solution Approach 1:
The patent transitions from a planar 2D arrangement where sense amplifiers are on a separate substrate level to a 3D vertical arrangement where sense amplifiers are integrated at the same level as memory cells. This dimensional change eliminates long vertical routing paths through the substrate, reducing signal loss and timing delays while maintaining manufacturing precision through co-integration processes
2Quantity of substance
If vertical transistors are used in memory cells, then memory density is increased, but routing complexity and signal loss are exacerbated
Solution Approach 1:
The patent merges the memory cell level and sense amplifier level into a single integrated level, eliminating the need for complex long-distance vertical routing through the substrate. This co-integration approach reduces routing complexity and signal loss while preserving the high memory density enabled by vertical transistors
3Reliability
If larger vertical transistors are used to increase bit-line swing, then signal detection capability is improved, but device area increases
Solution Approach 1:
The patent implements preliminary signal conditioning by placing sense amplifiers immediately adjacent to memory cells at the same level, allowing the small bit-line swing signal to be detected and amplified before significant signal loss occurs during vertical routing. This eliminates the need for oversized transistors to generate larger initial swings, maintaining compact device area
Data Source
AI summary
Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.