3D Semiconductor Structure With Single-Crystal Via Connective Paths
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Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor density and performance due to limitations in Through-Silicon Via (TSV) density, alignment issues, and the need for high-temperature processing, which affects the reliability of interconnects and transistor performance.
Innovation Solution
The development of a 3D semiconductor device with a multilayer structure that includes single crystal silicon layers, transistors with single crystal channels, and metal layers for interconnections, utilizing a layer transfer process to achieve precise alignment and high-density interconnects without the need for high-temperature processing, enabling the formation of high-performance transistors with reduced parasitic capacitances and resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Through-Silicon Via (TSV) technology is used for 3D IC interconnections, then vertical connectivity between stacked chips is achieved, but TSV density is limited due to large landing pad requirements and alignment issues
Solution Approach 1:
The patent transitions from planar 2D chip interconnections to three-dimensional stacked architecture, enabling vertical interconnections through TSVs. This dimensional change allows multiple computational layers to be stacked, dramatically increasing interconnection density and enabling higher TSV densities by utilizing the vertical dimension for signal routing between chip layers
Solution Approach 2:
The patent implements preliminary alignment mark formation and bonding interface preparation before the actual wafer bonding process. Alignment marks are pre-formed on bonding interfaces, and bonding surfaces are prepared with appropriate textures or patterns, enabling precise alignment to be achieved during the bonding process and thereby increasing TSV density while maintaining manufacturing precision
2Reliability
If high-temperature processing is used to form transistors and interconnects, then device performance is improved, but interconnect reliability deteriorates due to thermal stress and metal diffusion
Solution Approach 1:
The patent segments the fabrication process into distinct temperature zones: low-temperature processes (below 400°C) are used for forming temperature-sensitive interconnect structures and bonding, while high-temperature processes are reserved for specific transistor formation steps. This segmentation allows interconnect reliability to be maintained by avoiding excessive thermal stress during critical bonding and interconnect formation stages
Solution Approach 2:
The patent introduces barrier metal layers and diffusion阻挡 structures as intermediary elements between metal interconnects and semiconductor substrates. These intermediary layers prevent direct metal diffusion into the substrate during high-temperature processing, thereby maintaining interconnect reliability even when high-temperature steps are required for transistor formation
3Productivity
If device size is reduced to increase density, then area cost is reduced and device speed is enhanced, but interconnect wiring becomes the dominant limitation on performance
Solution Approach 1:
The patent utilizes three-dimensional stacked architecture with vertical TSV interconnections to reduce the horizontal wiring length between functional blocks. By stacking multiple computational layers vertically and connecting them through short TSVs, the patent dramatically reduces the total interconnect wiring length compared to traditional planar 2D layouts, thereby overcoming the interconnect bottleneck that limits further performance scaling at small device dimensions
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the via includes a contact to at least one of the transistors.