3D SiP Dual-Sided Routing to Reduce Package Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller and more creative packaging techniques for semiconductor dies, particularly in reducing package warpage and increasing integration density, as existing methods struggle to balance component density and structural integrity in Package-on-Package (PoP) technology.
Innovation Solution
A dual-sided routing approach is implemented in a semiconductor system-in-package (SiP) structure, where one redistribution structure has a fan-out design and the other is carrier-type, with a fan-out redistribution structure on one side and a substrate-type on the other, embedded in an encapsulant to form a thinner and stronger package with reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Package-on-Package (PoP) technology is used to increase integration density, then component density is improved, but package warpage increases
Solution Approach 1:
The patent divides the routing function into two separate redistribution structures located on opposite sides of the semiconductor die. This segmentation allows each redistribution structure to be independently optimized and positioned to balance the mechanical stresses, thereby reducing package warpage while maintaining high component density through the stacked PoP configuration.
Solution Approach 2:
The patent employs asymmetric routing designs where the first and second redistribution structures have different configurations, trace layouts, or positioning relative to the die. This asymmetry is intentionally introduced to counterbalance the thermal and mechanical expansion differences between stacked packages, effectively reducing warpage while achieving high integration density.
2Quantity of substance
If iterative reduction of minimum feature size is implemented to improve integration density, then more components can be integrated into a given area, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar routing to three-dimensional dual-sided routing by placing redistribution structures on both the front and back sides of the semiconductor die. This dimensional change allows routing paths to be distributed across multiple planes, reducing the complexity of any single layer while achieving higher integration density through vertical stacking.
3Productivity
If thinner package structure is achieved through dual-sided routing, then integration efficiency is improved, but structural strength may be compromised
Solution Approach 1:
The patent employs composite construction by combining multiple redistribution structures, die layers, and encapsulant materials in a stacked configuration. This composite approach allows the thin package structure to maintain structural integrity through the distributed reinforcement provided by the dual-sided routing layers and encapsulant, achieving both thinness and strength simultaneously.
Data Source
AI summary
A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.