3D Frontside SiPM Architecture Without TSVs for Low Jitter
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Solution Overview
Problem
Current single-photon avalanche diode (SPAD) arrays face issues with timing jitter, crosstalk noise, and complex manufacturing due to the use of through-silicon-vias (TSVs) in frontside illumination (FSI) architectures, which reduce the photosensitive surface area and increase manufacturing costs, while backside illumination (BSI) architectures limit timing jitter reduction due to carrier drift distances.
Innovation Solution
A thinned down frontside 3D SPAD array architecture with direct interconnect layers between SPADs and CMOS readout, eliminating the need for TSVs and incorporating extended isolation trenches to optically and electrically isolate SPAD cells, minimizing crosstalk and allowing direct backside connection, thereby reducing timing jitter and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If through-silicon-vias (TSVs) are used in frontside illumination SPAD architecture, then electrical connection between SPAD and readout circuitry is achieved, but photosensitive surface area is reduced and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D connection architecture to 3D vertical integration by stacking the SPAD array and readout circuitry on separate tiers, connected through vertical interconnects. This dimensional change eliminates the need for TSVs in the traditional sense while achieving electrical connection without compromising the photosensitive surface area of the SPADs.
Solution Approach 2:
The device is segmented into distinct functional tiers: the SPAD array tier with photosensitive surfaces, and the readout circuitry tier, connected through controlled vertical interconnect structures. This segmentation allows each tier to be optimized independently, preserving photosensitive area while managing manufacturing complexity through modular fabrication processes.
2Measurement precision
If through-silicon-vias (TSVs) are used for electrical connection, then SPAD array can be connected to readout circuitry, but timing jitter increases due to non-uniform electrical paths
Solution Approach 1:
The patent implements uniform electrical potential distribution across the SPAD array through carefully designed interconnect structures on the readout tier. Each SPAD cell is connected through matched impedance paths, ensuring uniform signal propagation characteristics and minimizing timing jitter variations across the array.
Solution Approach 2:
The readout circuitry tier is designed to maintain equipotential conditions for signal reference, with ground and power distribution networks optimized to minimize potential differences across the array. This equipotential design ensures that timing measurements are not affected by voltage drops or potential variations in the electrical paths.
3Area of stationary object
If SPAD cells are densely packed to increase detection area, then photosensitive fill-factor increases, but crosstalk noise between adjacent cells increases
Solution Approach 1:
Optical absorption layers are introduced as intermediary materials between adjacent SPAD cells in the vertical stack. These layers selectively absorb photons that would otherwise cross-talk between neighboring cells, allowing dense packing of SPADs while suppressing optical crosstalk noise through the mediating absorption function.
Solution Approach 2:
The patent employs composite material structures combining different semiconductor layers with varying optical absorption characteristics. By stacking materials with complementary properties, the design achieves high photosensitive fill-factor while using specific layer combinations to absorb stray photons and prevent crosstalk between densely packed cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves low timing jitter and reduced crosstalk noise, enhancing the photosensitive fill-factor and simplifying the manufacturing process, while maintaining high detection efficiency and resolution for various wavelengths.
Implementation Method 1
The single-photon avalanche diode (SPAD) is a photodiode polarized above the breakdown voltage in a quiet (zero current) metastable state. Once a photoelectron or a thermally excited or released electron enters the photodetector, the metastable state is lost as the current rises swiftly to a detectable macroscopic steady level.
Implementation Method 2
Once a photoelectron or a thermally excited or released electron enters the photodetector, the metastable state is lost as the current rises swiftly to a detectable macroscopic steady level.
Implementation Method 3
opto-electrical insulation barriers filling a space defined by trench walls extending through the first and second material layer to optically and electrically insulate individual SPAD cells of the SPAD array from one another
Data Source
AI summary
This disclosure pertains to a new thinned down frontside illuminated 3D SiPM architecture, e.g. a Photon-to-Digital Converter, with direct interconnect layers between the SPAD and the CMOS. The described architecture removes the need to have through-silicon-vias. Additionally, this new architecture also provides low jitter operation of the SPADs. The architecture described herein, with extended isolation trenches through the entire thickness of the thinned down SPAD substrate, enables both the SPAD cell to be electrically and optically isolated from the other SPAD cells. As such, the crosstalk is minimized and direct backside connection is possible.