3D SmartNIC Spatial Distribution for Scalability

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Solution Overview

Problem

Current SmartNICs spatially disaggregate compute, networking, and storage functions in two dimensions, limiting scalability to meet future bandwidth demands and inefficiently handling metadata and data movement due to repetitive buffering, leading to resource inefficiencies.

Innovation Solution

A 3D SmartNIC with multiple stacked layers that spatially distribute accelerator functions in three dimensions, using a sequencer to coordinate traffic flow between accelerator functions, reducing latency and repetitive buffering through direct communication between layers and centralized packet buffering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If functions are spatially disaggregated in two dimensions using chiplets or monolithic dies, then current SmartNIC functionality is achieved, but scalability to meet future bandwidth demands is severely limited

Engineering Contradiction:
ImprovescalabilityVSAvoidspatial distribution architecture
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent transitions from traditional 2D spatial arrangement of chiplets or monolithic dies to a 3D stacked architecture where multiple layers of accelerator functions are vertically arranged. This dimensional change enables significantly higher bandwidth capacity and scalability while maintaining manageable complexity through modular layer design, directly resolving the contradiction between scalability and device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If metadata contains action verbs and tenant information for each processing stage, then processing accuracy is improved, but metadata overhead becomes significant relative to data being processed

Engineering Contradiction:
Improveprocessing accuracyVSAvoidmetadata overhead
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent extracts and separates metadata handling from the main data flow by implementing dedicated metadata buffers and processing paths within the 3D stacked architecture. This allows metadata to be processed independently and efficiently, reducing its overhead impact on the overall data transmission while maintaining processing accuracy through preserved action verb and tenant information.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If data and metadata are repetitively buffered as traffic migrates through pipeline stages, then processing flexibility is maintained, but resource usage efficiency decreases

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidresource usage efficiency
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent implements preliminary buffering actions at specific strategic locations within the 3D stacked pipeline stages, preparing data and metadata for upcoming processing operations before they are actually needed. This proactive approach maintains processing flexibility while minimizing repetitive buffering by pre-positioning data where it will be most efficiently processed, thereby improving resource usage efficiency.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If accelerator functions are distributed across multiple layers, then physical and logical coupling between pipeline stages is improved, but device complexity increases

Engineering Contradiction:
Improvecoupling between pipeline stagesVSAvoidmulti-layer architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the accelerator functions into distinct modular layers, each handling specific processing tasks. This segmentation improves reliability by creating well-defined interfaces and coupling between pipeline stages while managing complexity through standardized module designs that can be independently optimized and assembled, directly addressing the contradiction between coupling quality and architectural complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12147369B2Spatial distribution in a 3D data processing unit
Publication Date: 2024.11.19 XILINX INC
  • US12147369B2 patent drawing
  • US12147369B2 patent drawing
  • US12147369B2 patent drawing

AI summary

The embodiments herein describe a 3D SmartNIC that spatially distributes compute, storage, or network functions in three dimensions using a plurality of layers. That is, unlike current SmartNIC that can perform acceleration functions in a 2D, a 3D Smart can distribute these functions across multiple stacked layers, where each layer can communicate directly or indirectly with the other layers.