3D SoC Atomic Handler for Disaggregated Memory Transactions
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Solution Overview
Problem
Conventional systems fail to address the handling of atomic transactions in a disaggregated 3D-structured System on Chip (SoC) architecture, particularly in graphics processors with a modular design.
Innovation Solution
Implement a disaggregated 3D-structured SoC architecture that includes a package substrate with a bottom-level cache die interfaced with a compute die and a system die, utilizing Compute Express Link (CXL) interconnects to handle atomic operations in system and local memory, supported by an atomic handler to manage transactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a disaggregated 3D-structured SoC architecture is implemented, then device complexity and adaptability are improved, but handling atomic transactions becomes more difficult
Solution Approach 1:
An atomic handler is introduced as an intermediary component between the compute engine and the disaggregated memory system. The atomic handler receives atomic operation requests, determines whether they target local or system memory, and routes them appropriately. This mediator resolves the complexity of atomic transaction handling in the disaggregated architecture by centralizing the decision-making logic and providing a unified interface for atomic operations.
2Productivity
If atomic operations are handled in disaggregated memory, then productivity is improved, but device complexity increases
Solution Approach 1:
The memory system is segmented into local memory (bottom-level cache die) and system memory (remote memory), each with dedicated access paths. The atomic handler segments atomic operation handling by determining the target memory type and routing requests accordingly. This segmentation allows parallel processing of atomic operations on different memory types, improving throughput while managing complexity through clear separation of responsibilities.
Solution Approach 2:
The atomic handler is designed as a universal component that can handle atomic operations on both local and system memory through a unified interface. It supports multiple CXL protocols (CXL.io, CXL.cache, CXL.mem) and can process various types of atomic operations (read-modify-write, compare-and-swap, etc.). This multi-functionality improves productivity by providing consistent atomic operation support across the entire disaggregated memory hierarchy while avoiding the need for separate handling logic for each memory type.
Data Source
AI summary
In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.