3D-SOC Image Sensor Package for Signal Latency Reduction
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Solution Overview
Problem
Conventional image sensor systems in mobile devices face inefficiencies due to long signal travel paths, limited processing capabilities, and excessive space consumption, as well as delayed feedback and high resource usage in digital image processing, which are exacerbated by the reliance on separate processor and image sensor components.
Innovation Solution
A 3D-SOC integration of photo detector assemblies with integrated processors and converters on separate substrates, where each assembly includes a photo detector, an analog-to-digital converter, and a processor, fabricated using CMOS processes to reduce signal latency and improve processing power within a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a stacked SIP configuration is used to package processor with image sensor, then the processor can process image sensor signals, but the signal travel path becomes long (through wirebonding, interposer, and more wirebonding) reducing efficiency
Solution Approach 1:
The patent merges the processor and image sensor die into a single System-On-Chip (SOC) structure, eliminating the need for separate packaging components like wirebonds and interposers. The processor is directly integrated on the same die as the image sensor, creating unified signal pathways that dramatically reduce travel distance while maintaining full processing capability.
2Ease of manufacture
If the sensor die includes basic pre-processing functions, then analog signals can be converted to digital signals, but post processing capability is absent
Solution Approach 1:
The patent combines both pre-processing and post-processing functions into a single integrated processor on the image sensor die. This unified processor architecture enables the sensor to perform not only analog-to-digital conversion but also advanced post-processing operations such as noise reduction, sharpness enhancement, and other image quality improvements that were previously unavailable in compact sensor designs.
3Length of moving object
If a 2D SOC configuration is used to form processor and image sensor on the same die, then signal travel distance is reduced, but processor area is significantly limited thus limiting processing capabilities
Solution Approach 1:
The patent transitions from a traditional 2D SOC layout to a three-dimensional stacked architecture. By vertically stacking the processor over the image sensor die and using through-silicon vias (TSVs) for inter-layer connections, the design achieves both short signal paths and adequate processor area. This 3D integration allows the processor to occupy vertical space rather than lateral space, enabling full processing capabilities without compromising signal travel distance.
4Volume of moving object
If 2.5D/3D packaging techniques are used to mount separately fabricated modules on top of one another, then overall size is reduced somewhat and signal travel distance is reduced somewhat, but careful integration is still required and size reduction is limited
Solution Approach 1:
The patent merges the processor and image sensor into a single monolithic die structure rather than using separate packaged modules. This integration eliminates the need for complex 2.5D/3D packaging processes, including module fabrication, bonding, and alignment. The unified die structure achieves maximum size reduction while dramatically simplifying the manufacturing process and eliminating integration complexity associated with multi-module stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces signal latency, enhances processing power, and minimizes size, allowing for efficient and fast image processing directly within the image sensor chip, freeing up the application processor for other tasks and reducing resource consumption.
Implementation Method 1
Each of the photo detector assemblies comprises a photo detector formed on or in a second substrate and configured to generate an analog signal in response to received light
Data Source
AI summary
An image sensor that comprises a first substrate and a plurality of photo detector assemblies disposed on or in the first substrate. Each of the photo detector assemblies comprises a photo detector formed on or in a second substrate and configured to generate an analog signal in response to received light, a converter formed on or in a third substrate, wherein the converter is electrically coupled to the photo detector and includes circuitry for converting the analog signal to a digital signal, a processor formed on or in a fourth substrate, wherein the processor is electrically coupled to the converter and includes circuitry for processing the digital signal.