3D SOC PMUT Array Layout for High-Density Ultrasonic Integration
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Solution Overview
Problem
Conventional ultrasonic transducers face challenges in miniaturization due to excessive metal wiring, parasitic resistance, and capacitance, which affect performance and make it difficult to achieve high-density integration and high-resolution imaging.
Innovation Solution
A 3D System-On-Chip (SOC) architecture is introduced, where a PMUT array is stacked on top of a CMOS unit with vertical interconnections through metal lead vias and hybrid bonding, eliminating peripheral bonding pads and using Through-Silicon Vias (TSVs) for connection to a printed circuit board, reducing metal wiring length and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a planar CMOS-based MEMS technique is used to increase ultrasonic transducer array density, then the viewing field and measurement accuracy are improved, but the length and density of metal lead wires increase rapidly, occupying excessive chip area and causing voltage drop and electrical interference
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. The PMUT array and CMOS circuit are positioned on different vertical layers, with interconnections achieved through vertical Through-Silicon Vias (TSVs) rather than extensive planar metal lead wires. This dimensional change dramatically reduces the chip area occupied by interconnects while maintaining high array density and measurement precision.
2Measurement precision
If the density of ultrasonic transducer array is increased, then the resolution of medical imaging is improved, but the number and length of metal lead wires increase, leading to increased parasitic resistance and capacitive delay effects
Solution Approach 1:
By stacking the PMUT array and CMOS circuit on separate layers and using vertical TSV interconnections, the patent minimizes the length and number of metal lead wires. This dramatically reduces parasitic resistance and capacitive delay effects, thereby maintaining electrical performance reliability even as array density and imaging resolution are increased.
Solution Approach 2:
The patent segments the system into distinct functional layers: the PMUT array layer for sensing and the CMOS circuit layer for processing, connected through vertical TSVs. This segmentation allows each layer to be optimized independently while minimizing inter-layer interference and parasitic effects, preserving electrical performance at high array densities.
3Ease of manufacture
If conventional mechanical cutting and metal interconnecting methods are used for piezoelectric ceramic crystals, then the transducer can be manufactured, but the yield is low, mechanical damages occur easily, and mass production is difficult
Solution Approach 1:
The patent replaces conventional mechanical cutting and interconnecting methods with a semiconductor fabrication process. The PMUT array is formed using standard CMOS-compatible processes including photolithography, sputtering, and TSV formation, enabling high-yield mass production without mechanical damage to the piezoelectric elements.
4Measurement precision
If the size of piezoelectric crystal is decreased to meet high-resolution imaging requirements, then the imaging resolution is improved, but the machining accuracy is limited by conventional methods
Solution Approach 1:
The patent replaces mechanical cutting with precision semiconductor fabrication techniques. The PMUT array elements are defined by photolithography patterns and formed through controlled sputtering and etching processes, achieving machining accuracy at the micrometer and sub-micrometer scale that is impossible with conventional mechanical methods, thereby enabling high-resolution imaging with small element sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly miniaturizes the ultrasonic transducer array, improves integration density, reduces parasitic effects, and enhances performance, making it suitable for high-resolution medical imaging and portable applications.
Implementation Method 1
a piezoelectric material layer (115), wherein a bottom metal layer (112) and a top metal layer (114) corresponding to the piezoelectric material layer (115) are arranged above and below the piezoelectric material layer (115) respectively
Data Source
AI summary
The present invention discloses an SOC PMUT suitable for high-density system integration, an array chip and a manufacturing method thereof. With the SOC PMUT suitable for high-density system integration, vertical stacking and monolithic integration of a SOC PMUT array with CMOS auxiliary circuits is realized by means of direct bonding of active wafers and a vertical multi-channel metal wiring structure; in addition, the extension to the package layer is implemented by means of TSVs, without any bonding mini-pad on the periphery of the array for communication with the CMOS. Thus, the bottleneck of metal interconnections in conventional ultrasonic transducers is overcome, the chip area occupied by metal interconnections in ultrasonic transducers is greatly reduced, the metal wiring length is reduced, thus the resulting adverse effects of an electrical parasitic effect on the performance of the ultrasonic transducer array are reduced.