3D SoIC Heat Dissipation Layout for Dense Memory Stacks
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Solution Overview
Problem
Three-dimensional system on integrated chip (3D SoIC) structures face high heat density and poor thermal dissipation performance, leading to electromigration and reliability issues due to increased chip density and varying thermal tolerances among different materials, which can result in thermo-mechanical stress and reduced chip performance.
Innovation Solution
The implementation of thermal interface material (TIM) rings and vertical conductive structures in dummy and molding regions, as well as within active chip areas, to create additional heat dissipation paths, utilizing materials like silver, aluminum nitride, and thermally conductive materials to channel heat away from high heat output areas to a heat sink.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional system on integrated chip structures with increased chip density are used, then chip density is improved, but thermal dissipation performance deteriorates
Solution Approach 1:
The patent transitions from two-dimensional heat dissipation to three-dimensional heat dissipation by stacking multiple chip layers vertically. Thermal interface material rings are positioned between stacked chips to conduct heat away from each layer, enabling effective thermal management in the vertical dimension while maintaining high chip density.
Solution Approach 2:
Thermal interface material rings serve as intermediary elements between stacked chips. These rings facilitate heat transfer from the chips to the surrounding thermal management structures, acting as a mediator that enables efficient thermal dissipation without compromising chip density.
2Productivity
If increased chip density is implemented, then productivity is improved, but reliability deteriorates due to electromigration and thermal stress
Solution Approach 1:
By implementing vertical stacking with thermal interface material rings positioned between layers, the patent enables three-dimensional heat dissipation that effectively manages thermal stress and prevents electromigration, thereby maintaining reliability while achieving high chip density and productivity.
Solution Approach 2:
Thermal interface material rings are strategically positioned at specific locations between stacked chips where heat generation is most intense. This localized approach addresses thermal management needs at critical points, preventing reliability issues while maintaining overall system productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the average operating temperature of memory chips below 90°C, improving the thermal dissipation efficiency and addressing reliability concerns by distributing heat more evenly and reducing thermo-mechanical stress across the 3D SoIC structure.
Implementation Method 1
thermal interface material (TIM) rings... to create additional heat dissipation paths... to channel heat away from high heat output areas to a heat sink
Data Source
AI summary
The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.