3D Source Follower Transistor Structure for Faster Low-Noise Image Sensors
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Solution Overview
Problem
As pixel count increases in image sensors, bitline setting time also increases due to higher bitline loading, leading to challenges in maintaining high frame rate operation without introducing noise or increasing pixel size.
Innovation Solution
The implementation of source follower transistors with a large effective channel width, achieved through non-planar structures and trench isolation techniques, enhances transconductance and reduces Random Telegraph Signal (RTS) noise without increasing pixel size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the source follower channel length is shortened to increase transconductance, then the operating speed is improved, but Random Telegraph Signal (RTS) noise increases
Solution Approach 1:
The patent transitions from a conventional planar channel structure to a three-dimensional FinFET structure. The channel is formed as a vertical fin extending from the substrate surface, creating a multi-dimensional conduction path. This dimensional change allows the channel length to be effectively shortened for speed improvement while the fin width and height provide sufficient channel width to maintain low noise performance.
Solution Approach 2:
The channel is segmented into multiple fins rather than using a single planar channel. The source follower transistor incorporates several parallel fins, each contributing to the total channel width. This segmentation allows the effective channel width to be increased without proportionally increasing the pixel area, thereby maintaining low noise while achieving high transconductance.
2Speed
If the source follower channel width is increased to increase transconductance, then the operating speed is improved, but the pixel size increases
Solution Approach 1:
The patent utilizes vertical dimension by forming fins that extend upward from the substrate. The channel width is effectively increased through the fin height and the number of fins, rather than expanding the planar footprint. This allows high transconductance to be achieved while maintaining compact pixel dimensions suitable for high-resolution imaging.
Solution Approach 2:
The FinFET structure concentrates the channel conduction in a localized vertical fin region, allowing the channel width to be effectively increased through fin geometry rather than lateral expansion. The source follower transistor achieves high transconductance through optimized fin dimensions while occupying minimal pixel area.
3Productivity
If more transistors are integrated to handle higher pixel counts, then the image sensor resolution is improved, but the bitline setting time increases
Solution Approach 1:
The patent changes the key transistor parameter from conventional planar geometry to FinFET structure, which fundamentally alters the transconductance characteristics. The FinFET source follower provides superior transconductance per unit area, enabling faster bitline charging and reduced setting time. This parameter change allows the sensor to handle higher pixel counts without proportionally increasing the bitline setting time.
Data Source
AI summary
An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.