3D Sidewall Spacer Formation for Uniform FinFET Doping
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Solution Overview
Problem
Existing methods for forming ultra-shallow dopant regions in semiconductor devices, such as FinFETs and tri-gate FETs, face challenges with non-uniform doping and lattice damage, especially in 3-dimensional structures, due to limitations in ion implantation and plasma doping technologies.
Innovation Solution
A method involving the deposition of multiple dielectric layers on a substrate, followed by anisotropic and isotropic etching to form 3D spacers, and subsequent solid-state diffusion of dopants through these spacers to create uniform dopant regions, using techniques like CVD, ALD, and thermal treatment to control dopant distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to form ultra-shallow dopant regions, then doping can be achieved, but non-uniform doping and lattice damage occur especially in 3-dimensional structures
Solution Approach 1:
The patent replaces ion implantation (a mechanical/physical bombardment process) with a chemical deposition process. A dopant-containing dielectric layer is deposited conformally over the 3D structure using CVD or ALD, followed by thermal diffusion. This substitution eliminates the mechanical damage caused by ion bombardment while achieving uniform dopant distribution in ultra-shallow regions.
Solution Approach 2:
The patent changes the doping mechanism from direct ion implantation to thermal diffusion. By depositing a dopant-containing layer and then applying thermal energy, the dopants diffuse into the semiconductor material. This parameter change (from kinetic energy delivery to thermal energy delivery) enables uniform doping without lattice damage in 3D structures.
2Manufacturing precision
If conventional doping methods are used, then doping can be performed, but shadowing effects prevent uniform doping in complex semiconductor structures
Solution Approach 1:
The patent applies conformal deposition to create a dopant-containing dielectric layer that uniformly coats all exposed surfaces of the 3D structure. Each local region receives the same dopant concentration through the conformal layer, ensuring uniform doping quality across complex structures without shadowing effects. The subsequent thermal diffusion process further ensures uniform dopant distribution throughout the doped region.
3Reliability
If device dimensions are reduced and devices are spaced closer together, then improved electrical performance is obtained, but formation of doped regions becomes more challenging
Solution Approach 1:
The patent segments the doping process into distinct stages: (1) conformal deposition of a dopant-containing dielectric layer with controlled thickness, (2) thermal diffusion to transfer dopants into the semiconductor, and (3) removal of the dielectric layer. This segmentation enables precise control of dopant depth and concentration, achieving uniform doping in ultra-shallow regions required for scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of ultra-shallow, uniformly doped regions with reduced lattice damage, addressing non-uniformity and shadowing effects, and facilitating conformal doping in complex semiconductor structures.
Implementation Method 1
performing an anisotropic dry etching that removes portions of the second layer and the third layer
Implementation Method 2
performing an isotropic etching that selectively removes the second sidewall spacer
Implementation Method 3
heating the substrate to form a doped region in the raised feature by diffusion of a dopant from the dopant layer into the raised feature
Data Source
AI summary
A method of processing a substrate that includes: loading the substrate having a raised feature with at least two sidewalls exposed in a processing chamber; depositing a first layer over the substrate to cover a first portion of the two sidewalls; depositing a second layer over the first layer to cover a second portion of the two sidewalls; depositing a third layer over the second layer and the raised feature to cover a third portion of the sidewalls and a top surface of the raised feature; performing an anisotropic dry etching that removes portions of the second layer and the third layer, a remainder of the second layer forming a second sidewall spacer and a remainder of the third layer forming a third sidewall spacer; and performing an isotropic etching that selectively removes the second sidewall spacer to expose portions of the sidewalls of the raised feature.