3D SRAM Cell Layout With Backside Metal Interconnects
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration and improved electrical properties while maintaining reliability and speed, particularly in the design of static random access memory (SRAM) cells.
Innovation Solution
The semiconductor memory device incorporates a substrate with vertically stacked lower and upper active regions, featuring gate electrodes and contacts that are connected through metal layers, allowing for increased integration and improved electrical connectivity, along with a backside metal layer that includes power and ground lines, enabling efficient electrical connections and reduced complexity in the back-end-of-line layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar SRAM cell structures are used, then manufacturing process is simple, but integration density is low and cell area is large
Solution Approach 1:
The patent transitions from a conventional planar (2D) SRAM cell structure to a vertically stacked (3D) configuration. The lower and upper active regions are stacked vertically on the substrate, with gate electrodes extending in the vertical direction. This dimensional change enables higher integration density by utilizing the third dimension (depth) rather than only the planar surface area, thereby reducing the footprint of each SRAM cell while maintaining functionality.
Solution Approach 2:
The patent implements a nested structure where the upper active region is positioned above and overlaps with the lower active region in the vertical direction. The gate electrodes are nested within the vertical stack, with the lower gate electrode associated with the lower active region and the upper gate electrode associated with the upper active region. This nesting arrangement compactly packs multiple functional elements into a smaller vertical space, reducing overall cell area.
2Reliability
If more metal interconnect layers are added to improve electrical connectivity, then electrical properties improve, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent utilizes vertical stacking to improve electrical connectivity without proportionally increasing horizontal interconnect complexity. The lower and upper active regions are vertically positioned to enable direct vertical connections through the stack, reducing the need for lengthy lateral metal interconnects. This vertical arrangement shortens current paths and improves electrical properties while limiting the expansion of the interconnect network in the planar direction.
Solution Approach 2:
The patent segments the SRAM cell into distinct lower and upper active regions with separate gate electrodes (lower gate electrode and upper gate electrode). This segmentation allows independent control and optimization of electrical pathways for each region. The lower active contact and upper active contact provide separate access points to the lower and upper source/drain regions, enabling flexible interconnection schemes that improve electrical connectivity without requiring a monolithic complex interconnect structure.
3Area of stationary object
If vertically stacked active regions with overlapping contacts are implemented, then integration density increases and cell area reduces, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses alignment precision challenges by moving the overlapping contact arrangement into the vertical dimension rather than requiring precise lateral alignment. The upper active contact and lower active contact are positioned to overlap when viewed from the top, but their precise vertical stacking is achieved through sequential formation processes. This vertical separation of alignment-critical features reduces the stringent lateral alignment precision requirements compared to purely planar overlapping structures.
Data Source
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AI summary
A semiconductor memory device comprising a substrate having first and second surfaces opposite to each other, a lower active region on the first surface and including a first lower gate electrode and a first lower active contact, an upper active region on the lower active region and including a first upper gate electrode and a first upper active contact that vertically overlap at least a part of the first lower active contact, a first connection structure vertically connecting the first upper active contact to the first lower active contact, a first metal layer on the first surface, and a backside metal layer on the second surface. The first upper gate electrode and the first lower gate electrode are connected and form a first gate electrode. The first metal layer includes a first node line electrically connecting the first gate electrode to the first upper active contact.