3D SRAM via Low-Temperature Bonding and Segmentation
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Solution Overview
Problem
Conventional methods for manufacturing three-dimensional static random-access memory (SRAM) face challenges due to immature manufacturing techniques and deficient processing, leading to poor performance, heat dissipation, and low integration.
Innovation Solution
A method involving the manufacturing of multiple MOS transistors at low temperatures, bonding of monocrystalline silicon or germanium wafers, and the formation of insulating layers to create a three-dimensional SRAM structure with interconnection layers, using techniques such as silicon-to-silicon direct bonding and low-temperature processing to improve integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing techniques are used for three-dimensional SRAM, then the manufacturing process is simpler, but the manufacturing precision and quality are poor due to immature techniques and deficient processing
Solution Approach 1:
The manufacturing process is divided into multiple sequential stages: forming first semiconductor structure with MOS transistors, bonding first material layer, forming second semiconductor structure with low-temperature MOS transistors, bonding second material layer, and forming third semiconductor structure. Each stage uses appropriate techniques to ensure quality while managing complexity incrementally
Solution Approach 2:
MOS transistors are manufactured at low temperatures (below 450°C) before bonding the monocrystalline material layers. This preliminary action ensures transistor quality is established before the bonding process, allowing precise control of critical transistor parameters while maintaining manufacturing feasibility
2Shape
If multiple layers of vertical-channel field effect transistor are fabricated through epitaxy and polycrystalline deposition, then three-dimensional structure is achieved, but the manufacturing technique remains immature and processing is deficient
Solution Approach 1:
The patent changes the temperature parameter to below 450°C for manufacturing MOS transistors, which enables the use of monocrystalline silicon or germanium wafers through bonding instead of polycrystalline deposition. This parameter change transforms the manufacturing approach from immature polycrystalline techniques to precise monocrystalline processing while maintaining three-dimensional vertical-channel structure
Solution Approach 2:
The patent uses composite structure combining monocrystalline material layers (for high precision and quality) with low-temperature MOS transistor structures (for three-dimensional geometry). This composite approach achieves both the desired three-dimensional shape and high manufacturing precision by leveraging the strengths of different material systems
3Area of stationary object
If SRAM units are made three-dimensional to improve integration and performance, then area occupation is reduced, but manufacturing complexity and quality control become problematic
Solution Approach 1:
The patent transitions from planar two-dimensional SRAM layout to three-dimensional stacked architecture where multiple semiconductor structures are vertically stacked and interconnected through through-silicon vias. This dimensional change reduces area occupation while the low-temperature manufacturing approach ensures quality control is maintained through precise temperature management and sequential processing stages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures high-quality, three-dimensional SRAM with reduced area occupation, improved performance, and simplified manufacturing, addressing the limitations of conventional methods by combining mature transistor manufacturing and bonding techniques.
Implementation Method 1
bonding the first material layer to the first insulating layer through the silicon-to-silicon direct bonding process
Implementation Method 2
bonding a first material layer to the first insulating layer, and performing first thinning and first surface processing on the first material layer to form a first substrate layer; bonding a second material layer to the second insulating layer
Implementation Method 3
performing first thinning and first surface processing on the first material layer to form a first substrate layer; performing second thinning and second surface processing on the second material layer to form a second substrate layer
Implementation Method 4
manufacturing multiple first low-temperature MOS transistors at a low temperature on the first substrate layer; manufacturing multiple second low-temperature MOS transistors at a low temperature on the second substrate layer
Implementation Method 5
depositing metal in the through-hole to form an interconnection layer which interconnets the first semiconductor structure, the second semiconductor structure and the third semiconductor structure
Data Source
AI summary
The method for manufacturing a three-dimensional static random-access memory, including: manufacturing a first semiconductor structure including multiple MOS transistors and a first insulating layer thereon; bonding a first material layer to the first insulating layer to form a first substrate layer; manufacturing multiple first low-temperature MOS transistors at a low temperature on the first substrate layer, and forming a second insulating layer thereon to form a second semiconductor structure; bonding a second material layer to the second insulating layer to form a second substrate layer; manufacturing multiple second low-temperature MOS transistors at a low temperature on the second substrate layer, and forming a third insulating layer thereon to form a third semiconductor structure; and forming an interconnection layer which interconnets the first semiconductor structure, the second semiconductor structure and the third semiconductor structure.