3D SRAM Circuit Double Gate Transistor Layout
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Solution Overview
Problem
Current SRAM memory devices with transistors distributed over multiple levels face challenges in achieving improved electrical performances while maintaining a compact size, particularly in interconnection density and efficiency of operations such as reading and writing.
Innovation Solution
The integration of a SRAM memory device with a unique configuration where the lower gate electrodes of transistors are connected through a conductive polarization line, allowing for improved electrical performance by reducing interconnection density and enhancing writing and reading operations, utilizing a layout with double gate transistors and specific conductive via connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are distributed over several levels to increase density, then transistor density is improved, but interconnection complexity and electrical performance deteriorate
Solution Approach 1:
The patent merges the lower gate electrodes of multiple transistors (first transistor and second transistor) into a single common lower gate electrode structure. This consolidation reduces the number of separate interconnections required, simplifying the overall interconnection architecture while maintaining the benefits of multi-level transistor distribution for high density.
Solution Approach 2:
The common lower gate electrode serves multiple functions: it acts as the lower gate for both the first and second transistors simultaneously, and it is connected to the conductive polarization line that provides polarization voltage to enhance electrical performance. This multi-functional design reduces interconnection complexity while supporting high-density transistor arrangements.
2Ease of manufacture
If conventional SRAM layout is used, then manufacturing is simpler, but electrical performance and writing margin are insufficient
Solution Approach 1:
The patent extends the gate electrode structure into the vertical dimension by implementing a double gate configuration where the lower gate electrode is positioned in a lower semiconductor layer and the upper gate electrode is in an upper semiconductor layer. This three-dimensional arrangement improves electrical performance and writing margin while maintaining manufacturing feasibility through standard multi-layer semiconductor processing techniques.
Solution Approach 2:
The conductive polarization line acts as an intermediary element that connects to the common lower gate electrode and provides polarization voltage to enhance the electrical performance of the SRAM cell. This intermediary structure enables improved writing margin and read/write access times without requiring complete redesign of the manufacturing process.
3Quantity of substance
If interconnection density is high, then transistor integration is higher, but reading and writing access times increase
Solution Approach 1:
By merging the lower gate electrodes of the first and second transistors into a common structure connected to the conductive polarization line, the patent reduces the number of interconnection paths required. This consolidation shortens the effective signal paths for read and write operations, reducing access times while maintaining high transistor integration through multi-level stacking.
Data Source
AI summary
The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.