3D SRAM Structure with Layer Decoders to Eliminate Half-Selected Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced SRAM designs face inefficiencies due to unnecessary power consumption from half-selected memory cells when memory arrays are subdivided into banks, leading to dummy read behavior and increased surface area requirements.
Innovation Solution
A three-dimensional SRAM structure with multiple semiconductor layers, including layer decoder circuitry and word line driver circuits, allows for vertical extension of complementary bit line pairs and selective activation of word lines, ensuring only selected memory cells are powered during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory arrays are subdivided into banks, then surface area efficiency is improved, but power consumption increases due to half-selected memory cells
Solution Approach 1:
The patent transitions from a conventional 2D memory array layout to a 3D stacked architecture where multiple memory arrays are vertically stacked. This dimensional change allows independent word line control for each stacked array, enabling selective activation of only the targeted array during read/write operations. Consequently, half-selected memory cells in non-targeted arrays remain inactive, eliminating their power consumption while maintaining high density and surface area efficiency.
2Area of stationary object
If memory arrays are subdivided into banks, then surface area efficiency is improved, but dummy read behavior occurs
Solution Approach 1:
By stacking multiple memory arrays vertically and providing independent word line control for each array, the patent enables precise selection of the target array. This prevents dummy read behavior because only the selected array's word lines are activated, while other stacked arrays remain completely inactive. The 3D architecture thus eliminates the harmful effect of dummy reads that occur in 2D banked structures.
3Ease of manufacture
If conventional 2D SRAM structure is used, then manufacturing is simpler, but power consumption increases from half-selected cells
Solution Approach 1:
The patent employs a 3D stacked memory architecture where multiple memory arrays are vertically stacked with independent word line control for each array. This allows the system to activate only the specific stacked array being accessed, keeping other arrays in a low-power state. The result is a significant reduction in power consumption from half-selected cells while maintaining manufacturing feasibility through standard semiconductor fabrication processes adapted for 3D stacking.
Data Source
AI summary
Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.