3D 6T SRAM Pillar Layout for Dense Scaling Without Shorting
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Solution Overview
Problem
The challenge in microelectronic device design and fabrication is to increase the integration density of 6T SRAM cells by reducing the dimensions of individual features and the distance between neighboring features, while maintaining accurate fabrication and preventing electrical shorting.
Innovation Solution
The design incorporates a gate electrode that partially surrounds pillars, with conductive plugs and wordlines configured to provide electrical contact to multiple pillars, and elongate conductive features with an offset pattern to reduce resistance and prevent shorting, allowing for compact and scalable device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature dimensions are reduced to increase integration density, then device integration increases, but electrical resistance increases and performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to three-dimensional vertically-channelled transistors with gate electrodes that wrap around pillars. This dimensional change allows increased integration density while maintaining adequate current flow paths through the vertical channel structure, thereby improving electrical performance despite reduced feature dimensions.
Solution Approach 2:
The patent employs composite material structures including semiconductor pillars surrounded by gate electrodes, with insulative materials strategically placed. This composite architecture enables compact feature integration while maintaining electrical performance through optimized material combinations and spatial arrangements.
2Quantity of substance
If feature dimensions are reduced to increase integration density, then device integration increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into discrete segments: semiconductor pillars, gate electrodes, insulative structures, and contact regions. This segmentation enables modular fabrication where each component can be formed through dedicated processing steps, simplifying the overall manufacturing of compact three-dimensional structures.
Solution Approach 2:
By moving to vertical channels and wrap-around gate electrodes, the patent creates a three-dimensional architecture that, while compact, can be fabricated using sequential deposition and etching steps that build structures vertically rather than requiring complex lateral patterning at reduced dimensions.
3Quantity of substance
If contact features are placed closer to increase integration, then device integration increases, but shorting between contacts increases
Solution Approach 1:
The patent positions contact features at different vertical levels and uses insulative structures to spatially separate adjacent contacts. This three-dimensional arrangement allows contacts to be placed closer horizontally while maintaining electrical isolation through vertical spacing and insulative barriers, preventing shorting while increasing integration density.
Solution Approach 2:
Insulative structures are introduced as intermediary elements between adjacent conductive contacts and transistor components. These insulative materials provide electrical isolation and prevent shorting while enabling closer spacing of contact features, thus increasing integration without compromising reliability.
Data Source
AI summary
Microelectronic devices include at least one memory cell, each with six transistors collectively comprising six pillars grouped in pillar pairs and formed from a semiconductor material. Each of the pillar pairs includes a first and a second pillar. Gate electrodes are also included, with each gate electrode extending between and horizontally around a portion of the first pillar and a portion of the second pillar of a respective one of the pillar pairs. Conductive structures are electrically coupled to the six pillars. At least one of the conductive structures is in physical contact with more than one of the pillars of the microelectronic device. Related methods and electrical systems are also disclosed.