3D SRAM Nanosheet Etching With Smooth Sidewalls
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SRAM architectures and photonic integrated circuits face challenges in achieving high-density, low-loss waveguides and efficient integration of three-dimensional SRAM cells due to imperfections in fabrication processes, such as high line edge roughness and sidewall roughness, which affect transmission losses and yield in photonic quantum circuits.
Innovation Solution
The method involves Catalyst Influenced Chemical Etching (CICE) to fabricate vertical nanostructures with low line edge roughness and sidewall roughness, enabling the creation of three-dimensional SRAM devices with nanosheet FETs and FinFETs, and optical waveguides with smooth sidewalls, using a catalyst layer and etchant to form vertical nanostructures with specific dimensions and compositions, and selectively processing layers for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to fabricate waveguides, then manufacturing process is simple, but line edge roughness and sidewall roughness are high causing transmission losses
Solution Approach 1:
The patent replaces conventional mechanical/plasma etching methods with a chemical etching process using fluorinated plasma and hydrogen peroxide vapor. This chemical substitution achieves smooth sidewalls and low line edge roughness by utilizing chemical reactions rather than physical sputtering, directly resolving the contradiction between manufacturing simplicity and surface quality.
Solution Approach 2:
The patent changes the chemical parameters of the etching environment by introducing hydrogen peroxide vapor alongside fluorinated plasma. This parameter modification alters the etching chemistry to produce smoother surfaces with reduced roughness, thereby reducing transmission losses while maintaining process feasibility.
2Quantity of substance
If three-dimensional SRAM cells are integrated to increase density, then memory capacity increases, but fabrication imperfections increase causing yield reduction
Solution Approach 1:
The patent replaces conventional plasma etching with chemical etching using fluorinated plasma and hydrogen peroxide vapor. This substitution produces vertical nanostructures with significantly reduced sidewall roughness and line edge roughness, enabling high-density 3D SRAM integration while maintaining manufacturing precision and yielding defect-free structures.
3Productivity
If vertical nanostructures are fabricated with high aspect ratios, then device density increases, but sidewall roughness increases causing performance degradation
Solution Approach 1:
The patent replaces mechanical plasma etching with chemical etching using fluorinated plasma and hydrogen peroxide vapor. This chemical approach enables the fabrication of vertical nanostructures with high aspect ratios while maintaining smooth sidewalls and low roughness, resolving the contradiction between achieving high device density and maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the development of high-density, low-loss SRAM devices and photonic integrated circuits with reduced transmission losses, enhancing the integration of quantum circuits and improving the yield and performance of photonic devices.
Implementation Method 1
Catalyst Influenced Chemical Etching (CICE) is a catalyst-based etching method that can be used to fabricate features in semiconductors
Implementation Method 2
exposing the patterned catalyst layer to an etchant, where the patterned catalyst layer and the etchant cause etching of the semiconducting material
Data Source
AI summary
A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.